公开(公告)号：US20240284684A1

公开(公告)日：2024-08-22

申请号：US18426703

申请日：2024-01-30

Applicant: Kioxia Corporation

Inventor： Shinya WATANABE ,  Masahiro INOHARA ,  Tatsuo MIGITA ,  Masayuki MIURA

IPC: H10B80/00 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L21/78 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor device according to the present embodiment includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first upper surface on which a first electrode pad is formed. The second semiconductor chip has a first lower surface on which a second electrode pad directly joined to the first electrode pad is formed and a second upper surface that is opposite the first lower surface and on which a third electrode pad is formed. The area of the first lower surface is smaller than the area of the first upper surface. The barycenter of the first lower surface and the barycenter of the first upper surface are located at different positions in the in-plane direction of the first upper surface.

公开(公告)号：US20230307416A1

公开(公告)日：2023-09-28

申请号：US17940939

申请日：2022-09-08

Applicant: Kioxia Corporation

Inventor： Masayuki MIURA

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor device includes: a wiring substrate in which a wiring layer is provided; a first semiconductor chip that is provided above the wiring substrate and on a surface of which a first pad is formed, the surface being on a side closer to the wiring substrate; a second semiconductor chip that is provided on the first semiconductor chip through a first resin layer and on a surface of which a second pad is formed, the surface being on a side opposite the wiring substrate; a third semiconductor chip that is provided on the second semiconductor chip through a second resin layer and on a surface of which a third pad is formed, the surface being on the side closer to the wiring substrate; and a first wire connecting the first pad and the third pad; and a second wire connecting the second pad and the wiring substrate.

公开(公告)号：US20220301599A1

公开(公告)日：2022-09-22

申请号：US17475482

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Xu LI ,  Masayuki MIURA ,  Takayuki MIYAZAKI ,  Toshio FUJISAWA ,  Hiroto NAKAI ,  Hideko MUKAIDA ,  Mie MATSUO

IPC: G11C5/14 ,  H01L27/11556 ,  H01L27/11582 ,  H02M3/158 ,  G11C16/30

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

公开(公告)号：US20220285319A1

公开(公告)日：2022-09-08

申请号：US17459376

申请日：2021-08-27

Applicant: Kioxia Corporation

Inventor： Masayuki MIURA ,  Yuichi SANO ,  Kazuma HASEGAWA

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor device includes a first stacked body including first semiconductor chips stacked in a first direction and offset relative to each other in a second direction; a first columnar electrode coupled to the first semiconductor chip and extending in the first direction; a second stacked body arranged relative to the first stacked body in the second direction and including second semiconductor chips stacked in the first direction and offset relative to each other in the second direction; a second columnar electrode coupled to the second semiconductor chip and extending in the first direction; and a third semiconductor chip arranged substantially equally spaced to the first columnar electrode and the second columnar electrode.

公开(公告)号：US20220013477A1

公开(公告)日：2022-01-13

申请号：US17189718

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Soichi HOMMA ,  Tatsuo MIGITA ,  Masayuki MIURA ,  Takeori MAEDA ,  Kazuhiro KATO ,  Susumu YAMAMOTO

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

公开(公告)号：US20240421122A1

公开(公告)日：2024-12-19

申请号：US18743211

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Masayuki MIURA ,  Kazuma HASEGAWA ,  Yuichi SANO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/528 ,  H10B80/00

Abstract: A semiconductor device according to an embodiment includes a substrate, a plurality of first semiconductor chips, a plurality of first resins, and a second semiconductor chip. The substrate has a first surface. The plurality of first semiconductor chips are stacked while being displaced in a direction substantially parallel to the first surface. The plurality of first resins are provided on respective lower surfaces of the plurality of first semiconductor chips. The second semiconductor chip is provided on the first surface. At least one of the plurality of first resins is in contact with an upper surface of the second semiconductor chip.

公开(公告)号：US20240105539A1

公开(公告)日：2024-03-28

申请号：US18459841

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Naoya SHIROSHITA ,  Masayuki MIURA

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/295 ,  H01L23/562

Abstract: A semiconductor device includes: a wiring substrate; at least one first semiconductor element provided above the wiring substrate; a first resin layer configured to seal the first semiconductor element; and a second resin layer provided on an outer surface of the first resin layer. A Young's modulus of the second resin layer is greater than a Young's modulus of the first resin layer, and/or a linear thermal expansion coefficient of the second resin layer is greater than a linear thermal expansion coefficient of the first resin layer.

公开(公告)号：US20230324455A1

公开(公告)日：2023-10-12

申请号：US18209398

申请日：2023-06-13

Applicant: Kioxia Corporation

Inventor： Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Masayuki MIURA ,  Arata INOUE ,  Hiroyuki DOHMAE ,  Koichi NAKAZAWA ,  Mitoshi MIYAOKA ,  Kazuhito HAYASAKA ,  Tomoya SANUKI

IPC: G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2886 ,  G01R1/07342

Abstract: According to one embodiment, a wafer includes a substrate including a first region and a second region that do not overlap each other; a first chip unit and a second chip unit each arranged on the substrate; a first electrode and a second electrode each electrically connected to the first chip unit; and a third electrode and a fourth electrode each electrically connected to the second chip unit. The first electrode and the third electrode are arranged in the first region. The second electrode and the fourth electrode are arranged in the second region. The first region is independent of a region in which the first chip unit and the second chip unit are provided.

公开(公告)号：US20230282289A1

公开(公告)日：2023-09-07

申请号：US17899447

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Hitomi TANAKA ,  Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Masayuki MIURA ,  Yoshihiro OHBA

IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  H01L27/11563

CPC classification number: G11C16/26 ,  G06F3/0679 ,  G11C16/34 ,  H01L27/11563

Abstract: A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

公开(公告)号：US20230260966A1

公开(公告)日：2023-08-17

申请号：US17896796

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Masayuki MIURA

IPC: H01L25/065 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2225/06506 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor device includes a first stacked body provided above a substrate, and including a plurality of first semiconductor chips stacked on top of one another; and a second stacked body provided further above the first stacked body, and including a plurality of second semiconductor chips stacked on top of one another. The first semiconductor chips each have a first pad facing toward the substrate, and the second semiconductor chips each have a second pad facing away from the substrate.