公开(公告)号：US11282559B1

公开(公告)日：2022-03-22

申请号：US17201114

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Reika Tanaka ,  Masumi Saitoh ,  Takashi Maeda ,  Rieko Funatsuki ,  Hidehiro Shiga

IPC: G11C11/22 ,  H01L27/11597

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

公开(公告)号：US11049573B2

公开(公告)日：2021-06-29

申请号：US16802471

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Hidehiro Shiga ,  Hiroshi Maejima

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.

公开(公告)号：US11862246B2

公开(公告)日：2024-01-02

申请号：US17474904

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Yasuhito Yoshimizu ,  Keisuke Nakatsuka ,  Hideto Horii ,  Takashi Maeda

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/06 ,  G11C16/26 ,  G11C5/02 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/0433 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

公开(公告)号：US11715534B2

公开(公告)日：2023-08-01

申请号：US17459441

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Reiko Sumi ,  Reika Tanaka ,  Masumi Saitoh

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

公开(公告)号：US11579796B2

公开(公告)日：2023-02-14

申请号：US17197667

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Yuta Aiba ,  Hitomi Tanaka ,  Masayuki Miura ,  Mie Matsuo ,  Toshio Fujisawa ,  Takashi Maeda

IPC: G06F3/00 ,  G06F3/06

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of −40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of −40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

公开(公告)号：US11232843B2

公开(公告)日：2022-01-25

申请号：US17009376

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro Shiga ,  Takashi Maeda

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

Abstract: A nonvolatile semiconductor storage device includes a first channel layer including a first drain-side select transistor, a first source-side select transistor, and a first memory cell transistor, a second channel layer including a second drain-side select transistor, a second source-side select transistor, and a second memory cell transistor, a word line that functions as a gate electrode of the first and second memory cell transistors, and a controller. When a read operation is executed on the first memory cell transistor, the controller turns on the second drain-side select transistor and the second source-side select transistor, supplies a first voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and then, supplies a second voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned on.

公开(公告)号：US12125545B2

公开(公告)日：2024-10-22

申请号：US17689182

申请日：2022-03-08

Applicant: Kioxia Corporation

Inventor： Reiko Sumi ,  Takashi Maeda ,  Hidehiro Shiga

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/08

Abstract: A semiconductor memory device includes a driver that, in a write operation, applies a first voltage to a first select gate line, applies a second voltage lower than the first voltage to a second select gate line, applies a third voltage equal to or higher than the first voltage to a first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to a second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to a first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to a second dummy word line on a lowermost layer.

公开(公告)号：US11756946B2

公开(公告)日：2023-09-12

申请号：US17847528

申请日：2022-06-23

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Toshio Fujisawa ,  Hiroshi Maejima ,  Takashi Maeda

IPC: G11C16/04 ,  H01L25/18 ,  H01L23/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F3/06

CPC classification number: H01L25/18 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  G11C16/0483 ,  H01L2224/13016 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/73207

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

公开(公告)号：US11715527B2

公开(公告)日：2023-08-01

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka Ikegami ,  Hidehiro Shiga ,  Takashi Maeda ,  Rieko Funatsuki ,  Takayuki Miyazaki

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/20 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US11538536B2

公开(公告)日：2022-12-27

申请号：US17199718

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Shingo Nakazawa ,  Takashi Maeda

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/14

Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.