公开(公告)号：US11984394B2

公开(公告)日：2024-05-14

申请号：US17438728

申请日：2019-03-19

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Yasuhito Yoshimizu ,  Tomoya Sanuki ,  Fumitaka Arai

IPC: H10B41/27 ,  H01L23/522 ,  H01L23/535 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.

公开(公告)号：US11923325B2

公开(公告)日：2024-03-05

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Takashi Fukushima ,  Tatsuro Hitomi ,  Arata Inoue ,  Masayuki Miura ,  Shinichi Kanno ,  Toshio Fujisawa ,  Keisuke Nakatsuka ,  Tomoya Sanuki

IPC: H01L23/00 ,  G06F11/07 ,  H01L23/544

CPC classification number: H01L24/05 ,  G06F11/073 ,  G06F11/0751 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2924/14511

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US11450611B2

公开(公告)日：2022-09-20

申请号：US17015868

申请日：2020-09-09

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Yasuhito Yoshimizu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a substrate including two element regions that extend in a first direction parallel to a surface of the substrate and are adjacent to each other in a second direction crossing the first direction. The device further includes an interconnection layer provided above the substrate. The device further includes an insulator provided between the substrate and the interconnection layer. The device further includes a plug extending in the second direction and in a third direction crossing the first and second directions in the insulator, provided on each of the element regions, and electrically connected to the element regions and the interconnection layer.

公开(公告)号：US11756946B2

公开(公告)日：2023-09-12

申请号：US17847528

申请日：2022-06-23

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Toshio Fujisawa ,  Hiroshi Maejima ,  Takashi Maeda

IPC: G11C16/04 ,  H01L25/18 ,  H01L23/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F3/06

CPC classification number: H01L25/18 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  G11C16/0483 ,  H01L2224/13016 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/73207

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

公开(公告)号：US11422712B2

公开(公告)日：2022-08-23

申请号：US17121024

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Takashi Fukushima ,  Tatsuro Hitomi ,  Arata Inoue ,  Masayuki Miura ,  Shinichi Kanno ,  Toshio Fujisawa ,  Keisuke Nakatsuka ,  Tomoya Sanuki

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.

公开(公告)号：US11417642B2

公开(公告)日：2022-08-16

申请号：US17006378

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Toshio Fujisawa ,  Hiroshi Maejima ,  Takashi Maeda

IPC: G11C16/04 ,  H01L25/18 ,  H01L23/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F3/06

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

公开(公告)号：US20220149028A1

公开(公告)日：2022-05-12

申请号：US17580370

申请日：2022-01-20

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L23/528

Abstract: According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

公开(公告)号：US12204765B2

公开(公告)日：2025-01-21

申请号：US18181824

申请日：2023-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Toshio Fujisawa ,  Keisuke Nakatsuka

IPC: G06F12/00 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

公开(公告)号：US12142324B2

公开(公告)日：2024-11-12

申请号：US17681547

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Daisuke Fujiwara ,  Toshio Fujisawa

IPC: G11C16/08 ,  G11C8/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

Abstract: A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

公开(公告)号：US12068299B2

公开(公告)日：2024-08-20

申请号：US17580370

申请日：2022-01-20

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.