公开(公告)号：US08784931B2

公开(公告)日：2014-07-22

申请号：US12565448

申请日：2009-09-23

申请人： Kazuyoshi Ueno ,  Tetsuya Osaka ,  Nao Takano

发明人： Kazuyoshi Ueno ,  Tetsuya Osaka ,  Nao Takano

IPC分类号： H05K1/09 ,  B05D5/12

CPC分类号： C23C18/1893 ,  C23C18/1651 ,  C25D7/12 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76874 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/31663

摘要： A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer and an insulating interlayer portion made of SiO2. The method comprises the steps of treating, with a silane compound, a SiO2 surface of the insulating interlayer portion on which the diffusion layer is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. A capping layer may be formed on the wiring layer by electroless plating. Consequently, a diffusion prevention layer having good adhesive properties can be formed through a simple wet process, and, the wiring layer can directly be formed on this diffusion prevention layer by a wet process. The capping layer can also be directly formed on the wiring layer by electroless plating.

摘要翻译： 一种制造ULSI布线的方法，其中布线层经由扩散防止层和由SiO 2制成的绝缘夹层部分分别形成。 该方法包括以下步骤：用硅烷化合物处理要形成扩散层的绝缘层间部分的SiO 2表面，用含有钯化合物的水溶液进行催化，通过化学镀形成扩散防止层 ，然后在该扩散防止层上形成布线层。 可以通过无电解电镀在布线层上形成覆盖层。 因此，通过简单的湿法可以形成具有良好粘合性的扩散防止层，并且可以通过湿法直接在该扩散防止层上形成布线层。 覆盖层也可以通过无电镀直接形成在布线层上。

公开(公告)号：US07821135B2

公开(公告)日：2010-10-26

申请号：US11124804

申请日：2005-05-09

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.

摘要翻译： 具有改善的耐应力迁移电阻和可靠性的半导体器件包括其中形成有由阻挡金属膜和铜 - 银合金膜组成的下互连的绝缘膜，然后在其上形成层间绝缘膜。 在层间绝缘膜中形成由隔离金属膜和铜 - 银合金膜组成的上部互连。 下部和上部互连由铜 - 银合金制成，其含有的银的量超过银对铜的固溶极限。

公开(公告)号：US07566973B2

公开(公告)日：2009-07-28

申请号：US11489625

申请日：2006-07-20

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/7684

摘要： The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S100); forming a barrier metal layer on the whole surface of the insulating film (S102); forming a copper layer on the whole surface of the barrier metal layer so that the copper layer is embedded in the interconnect trench (S104); removing the copper layer outside the interconnect trench by polishing under a condition that the barrier metal layer is left on the surface of the insulating film (S106); selectively forming a cap metal layer on the copper layer formed in the interconnect trench after the step of removing the copper layer by polishing (S108); and flattening the cap metal layer by polishing (S110).

摘要翻译： 根据本发明的制造半导体器件的方法包括：在形成在半导体衬底上的绝缘膜中形成互连沟槽（S100）; 在绝缘膜的整个表面上形成阻挡金属层（S102）; 在阻挡金属层的整个表面上形成铜层，使得铜层嵌入在互连沟槽中（S104）; 在绝缘膜的表面上留下阻挡金属层的状态下，通过研磨来除去配线沟槽外的铜层（S106）。 在通过研磨去除铜层的步骤之后，在形成在所述互连沟槽中的铜层上选择性地形成帽金属层（S108）; 并通过研磨使盖金属层变平（S110）。

公开(公告)号：US06486559B1

公开(公告)日：2002-11-26

申请号：US09104044

申请日：1998-06-25

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L2348

CPC分类号： H01L21/76867 ,  H01L21/3146 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76823 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/7688 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The object of the present invention is to provide a copper wiring structure in which finely processed copper wiring in a wiring structure in grooves is steadily formed with a high reliability and a method for fabricating the same, wherein an electroconductive carbon layer is formed between the copper material—a copper wiring of a wiring structure in grooves in which the copper material is buried into a wiring groove or holes formed in the organic interlayer film mainly composed of carbon—and the organic interlayer film. This electroconductive carbon layer is formed after forming wiring grooves or holes in the desired region of the organic interlayer film, by a modification of the inner wall of the wiring grooves or holes by plasma irradiation. The copper wiring of the wiring structure in grooves as described above is formed by depositing copper on the electroconductive carbon layer.

摘要翻译： 本发明的目的是提供一种铜布线结构，其中槽中的布线结构中的精细加工的铜布线以可靠性稳定地形成并且制造方法，其中在铜 材料 - 铜材埋入布线槽的槽中的布线结构的铜布线或主要由碳 - 有机中间膜形成的有机中间膜中形成的孔。 通过等离子体照射改变布线槽或孔的内壁，在有机中间膜的所需区域中形成布线槽或孔之后形成该导电碳层。 如上所述的槽中的布线结构的铜布线通过在导电性碳层上沉积铜而形成。

公开(公告)号：US06482741B1

公开(公告)日：2002-11-19

申请号：US09377717

申请日：1999-08-20

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L244

CPC分类号： H01L21/76867 ,  H01L21/3146 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76823 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/7688 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The object of the present invention is to provide a copper wiring structure in which finely processed copper wiring in a wiring structure in grooves is steadily formed with a high reliability and a method for fabricating the same, wherein an electroconductive carbon layer is formed between the copper material—a copper wiring of a wiring structure in grooves in which the copper material is buried into a wiring groove or holes formed in the organic interlayer film mainly composed of carbon—and the organic interlayer film. This electroconductive carbon layer is formed, after forming wiring grooves or holes in the desired region of the organic interlayer film, by a modification of the inner wall of wiring grooves or holes by plasma irradiation. The copper wiring of the wiring structure in grooves as described above is formed by depositing copper on the electroconductive carbon layer.

摘要翻译： 本发明的目的是提供一种铜布线结构，其中槽中的布线结构中的精细加工的铜布线以可靠性稳定地形成并且制造方法，其中在铜 材料 - 铜材埋入布线槽的槽中的布线结构的铜布线或主要由碳 - 有机中间膜形成的有机中间膜中形成的孔。 在有机中间膜的期望区域中形成布线槽或孔之后，通过等离子体照射来改变布线槽或孔的内壁，形成该导电性碳层。 如上所述的槽中的布线结构的铜布线通过在导电性碳层上沉积铜而形成。

公开(公告)号：US06478935B1

公开(公告)日：2002-11-12

申请号：US09453061

申请日：1999-12-02

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： C25B1500

CPC分类号： H01L21/76873 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76882 ,  H01L2221/1089

摘要： An apparatus for plating a substrate includes plural plating baths that are each separately provided with (a) an individual temperature adjuster that includes a heater, a cooling jacket, and a temperature controller, or (b) an individual pressure application device for distorting the substrate.

摘要翻译： 一种用于电镀基板的设备包括多个电镀槽，每个电镀槽分别设置有（a）包括加热器，冷却套和温度控制器的单独的温度调节器，或者（b）用于使基板变形的单独的压力施加装置 。

公开(公告)号：US5227644A

公开(公告)日：1993-07-13

申请号：US709799

申请日：1991-06-03

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L29/778

CPC分类号： H01L29/7782

摘要： A field effect transistor comprising first and second electrodes, semiconductor layers connected to these electrodes to form a carrier channel between them and a control electrode is provided. Said semiconductor layers consisting essentially of: (a) a first semiconductor layer of a first semiconductor material having a low density of state of carrier formed on a substrate, (b) a second semiconductor layer of a second semiconductor material containing an impurity element and having a high density of state of carrier formed on the first semiconductor layer, and (c) a third semiconductor layer of a third semiconductor material having a low density of state of carrier formed on the second semiconductor layer, wherein the impurity element contained in the second semiconductor layer is of n-type when the carrier is an electron or of p-type when the carrier is a hole. By such combination as above of layers of low carrier density of state but high carrier mobility layers and a layer of low carrier mobility but high carrier density of state, higher concentration doping has been made possible. This is effective to realize a high performance FET suitable for larger scale integration.

摘要翻译： 提供了包括第一和第二电极的场效应晶体管，连接到这些电极的半导体层以在它们之间形成载流子通道和控制电极。 所述半导体层基本上由以下部分组成：（a）第一半导体材料的第一半导体层，其具有在衬底上形成的载流子状态较低的第一半导体层，（b）第二半导体层，其含有杂质元素，并具有 形成在第一半导体层上的载流子状态的高密度，以及（c）在第二半导体层上形成的具有低载流态状态的第三半导体材料的第三半导体层，其中包含在第二半导体层中的杂质元素 当载体是空穴时，当载体是电子或者是p型时，半导体层是n型的。 通过如上所述的低载流子浓度状态但具有高载流子迁移率层和低载流子迁移率层，但高载流子状态的层的组合，已经使得更高浓度的掺杂成为可能。 这对于实现适合于大规模集成的高性能FET是有效的。

公开(公告)号：US5098858A

公开(公告)日：1992-03-24

申请号：US545876

申请日：1990-06-29

申请人： Kazuyoshi Ueno ,  Kazuyuki Hirose

发明人： Kazuyoshi Ueno ,  Kazuyuki Hirose

IPC分类号： H01L29/812 ,  H01L21/28 ,  H01L21/285 ,  H01L21/329 ,  H01L21/338 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L29/66212 ,  H01L21/28575 ,  H01L21/28581 ,  H01L29/452 ,  H01L29/475 ,  Y10S148/139 ,  Y10S148/14 ,  Y10S438/971 ,  Y10S438/974

摘要： The method of manufacturing the metal-semiconductor junction in accordance with the present invention includes the step of forming a 2.times.2 surface superstructure in an ultrahigh vacuum by removing an oxide layer by means of a heat cleaning at temperatures not lower than 600.degree. C. while irradiating a (111) A or (111) B surface of a zincblende-type III-V compound semiconductor substrate with a beam of a group V element, the step of cooling the substrate down to room temperature while maintaining the surface superstructure and the step of depositing a metal on the surface.

摘要翻译： 根据本发明的制造金属 - 半导体结的方法包括通过在不低于600℃的温度下通过热清洗去除氧化物层而在超高真空中形成2x2表面上部结构的步骤，同时照射 具有V族元素束的锌辉石III-V族化合物半导体衬底的（111）A或（111）B表面，同时保持表面上层结构并将衬底冷却至室温的步骤，以及步骤 在表面上沉积金属。

公开(公告)号：US08069728B2

公开(公告)日：2011-12-06

申请号：US12244269

申请日：2008-10-02

申请人： John Goodfellow ,  Kazuyoshi Ueno ,  Milan Prodanovic ,  Koshi Yamamoto ,  Norihiro Maeda

发明人： John Goodfellow ,  Kazuyoshi Ueno ,  Milan Prodanovic ,  Koshi Yamamoto ,  Norihiro Maeda

IPC分类号： G01M7/00

CPC分类号： G01M7/022

摘要： Focusing on the criterion of “Energy save” or “Quiet noise” or other suitable operating parameter and considering the existing limitation of the operation of the electro-dynamic shaker system, apparatus for optimizing the operating condition of the vibration test system is proposed. The apparatus 100 measures the field current and drive current under the state that the desired vibration is fed to the specimen 20, and calculates the necessary force the shaker 1 should supply. Field current is supposed to be varied, and the necessary drive current is calculated based on the necessary force data. Further, the blower rotation is supposed to be varied, and the total power consumption at the coils and the blower is calculated. Also the temperatures of the field coil 4 and of the drive coil 10 is estimated and checked whether within the limitation. Then the optimal operating condition for the focused criterion is selected.

摘要翻译： 针对“节能”或“安静噪声”或其他合适的运行参数，并考虑到电动振动筛系统的现有操作限制，提出了优化振动试验系统运行状态的装置。 装置100在将期望的振动供给到试样20的状态下测量励磁电流和驱动电流，并计算振荡器1应提供的必要力。 励磁电流应变化，并根据必要的力数据计算必要的驱动电流。 此外，鼓风机旋转被认为是变化的，并且计算线圈和鼓风机的总功耗。 此外，在限制内，还估计和检查励磁线圈4和驱动线圈10的温度。 然后选择聚焦标准的最优运行条件。

公开(公告)号：US07741214B2

公开(公告)日：2010-06-22

申请号：US12325670

申请日：2008-12-01

申请人： Toshiyuki Takewaki ,  Kazuyoshi Ueno

发明人： Toshiyuki Takewaki ,  Kazuyoshi Ueno

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

摘要： In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.

摘要翻译： 在半导体装置中，在半导体基板的上方设置绝缘中间层，在绝缘中间层中形成有多个第一布线层和多​​个第二布线层。 第一布线层基本上由铜组成，并以大间距平行布置。 第二布线层基本上由铜组成，并以小的间距平行布置。 第一金属覆盖层形成在每个第一布线层上，第二金属覆盖层形成在每个第二布线层上。 第二金属覆盖层的厚度小于第一金属覆盖层的厚度。