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公开(公告)号：US06982200B2
公开(公告)日：2006-01-03
申请号：US10748286
申请日：2003-12-31
申请人： Junji Noguchi , Toshinori Imai , Tsuyoshi Fujiwara
发明人： Junji Noguchi , Toshinori Imai , Tsuyoshi Fujiwara
IPC分类号： H01L21/8242
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76832 , H01L21/76838 , H01L23/5223 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of manufacturing a semiconductor device which has reliable buried interconnects (wirings) and a reliable MIM capacitor. An interconnect and a capacitor bottom electrode are formed inside a hole made in six insulation films. Then a barrier insulation film is formed on the uppermost film (of the above six insulation films) including the interconnect and the top face of the bottom electrode. After two insulation films are formed above the barrier insulation film, a hole is made in the two insulation films and a capacitor top electrode is buried in that hole. The barrier insulation film also functions as a capacity insulation film for the capacitor. Then, after three other insulation films are formed on the upper film (of the above two insulation films) including the top face of the top electrode, a hole is made in the barrier insulation film, the two insulation films, and the three other insulation films, and another interconnect is buried in that hole.
摘要翻译： 公开了一种具有可靠的埋地互连（布线）和可靠的MIM电容器的半导体器件的制造方法。 在由六个绝缘膜制成的孔内形成互连和电容器底部电极。 然后在包括互连件和底部电极的顶面的最上面的膜（上述六个绝缘膜）上形成阻挡绝缘膜。 在阻挡绝缘膜上方形成两个绝缘膜之后，在两个绝缘膜中形成孔，并且在该孔中埋置电容器顶部电极。 阻挡绝缘膜还用作电容器的电容绝缘膜。 然后，在上电极（上述两个绝缘膜）的上部膜上形成三个绝缘膜之后，在隔离绝缘膜，两个绝缘膜和三个绝缘层中形成一个孔 电影，另一个互连被埋在那个洞里。
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公开(公告)号：US20080203531A1
公开(公告)日：2008-08-28
申请号：US12024140
申请日：2008-02-01
CPC分类号： H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.
摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。
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13.发明授权公开(公告)号：US06696357B2
公开(公告)日：2004-02-24
申请号：US10195716
申请日：2002-07-16
IPC分类号： H01L2160
CPC分类号： H01L24/05 , H01L21/76838 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05558 , H01L2224/05624 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.
摘要翻译： 要防止接合焊盘与接合焊盘之下的绝缘膜之间的剥离。 主要由W构成的层叠膜形成在形成于氧化硅膜中的孔内，其机械强度高于使用Al合金膜作为主导电层的布线层和焊盘，并且插入在布线 和接合垫。
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公开(公告)号：US20100181647A1
公开(公告)日：2010-07-22
申请号：US12750402
申请日：2010-03-30
CPC分类号： H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.
摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。
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公开(公告)号：US08183616B2
公开(公告)日：2012-05-22
申请号：US12873668
申请日：2010-09-01
申请人： Tsuyoshi Fujiwara , Toshinori Imai , Takeshi Saikawa , Yoshinori Kawasaki , Mitsuhiro Toya , Shunji Mori , Yoshiyuki Okabe
发明人： Tsuyoshi Fujiwara , Toshinori Imai , Takeshi Saikawa , Yoshinori Kawasaki , Mitsuhiro Toya , Shunji Mori , Yoshiyuki Okabe
IPC分类号： H01L29/94
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/87
摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.
摘要翻译： 提供了一种能够减小电容器的寄生电容同时减小电容器所占空间的技术。 通过在由下电极构成的电容器，电容绝缘膜和中间电极上形成电容器，由中间电极，另一电容绝缘膜和上电极构成的另一电容器形成堆叠结构。 由于中间电极具有台阶差，所以在电容器形成区域以外的区域中，中间电极和下部电极之间的距离以及中间电极与上部电极之间的距离变得比电容器形成区域的大。 例如，下电极与电容器形成区域中的电容绝缘膜直接接触，而在电容器形成区域以外的区域中，下电极不与电容器绝缘膜直接接触。
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公开(公告)号：US08551857B2
公开(公告)日：2013-10-08
申请号：US13034749
申请日：2011-02-25
申请人： Yuji Imamura , Tsuyoshi Fujiwara , Toyohiko Kuno
发明人： Yuji Imamura , Tsuyoshi Fujiwara , Toyohiko Kuno
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L23/53238 , H01L27/0688 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.
摘要翻译： 提供了通过少量步骤制造高电容和高精度MIM静电电容器的技术。 在第一层间绝缘膜上同时形成静电电容器和第二布线的下电极之后，在沉积在第一层间绝缘膜上的第二层间绝缘膜中形成开口部。 接下来，在包括开口部的内部的第二层间绝缘膜上顺序地沉积电容绝缘膜，第二金属膜和保护金属膜，并且在保护金属膜，第二金属膜和电容绝缘膜上 通过CMP法对第二层间绝缘膜进行抛光和去除，从而使电容绝缘膜，由第二金属膜制成的上电极和保护金属膜保持在开口部分。
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公开(公告)号：US07762021B2
公开(公告)日：2010-07-27
申请号：US10554832
申请日：2004-10-19
IPC分类号： B60J5/04
CPC分类号： B60J5/0402 , B60R13/04 , Y10T29/49622 , Y10T29/49915 , Y10T428/12354
摘要： A vehicular door sash includes a sash frame formed by subjecting a predetermined metal sheet to a roll molding process to have a predetermined cross section. The sash frame includes a groove portion for retaining a glass-run channel, a retainer portion for retaining a weather strip, a flange portion that connects the retainer portion and the groove portion and partially forms an outer surface of a door of a vehicle, and a sash molding configured to cover the flange portion. The flange portion has a first configuration in which the flange portion is not covered by the sash molding and a second configuration in which the flange portion is covered and compressed by the sash molding.
摘要翻译： 车门框包括通过对预定的金属板进行辊模制成而具有预定横截面而形成的窗框。 窗框包括用于保持玻璃通道的槽部分，用于保持耐候条的保持器部分，连接保持器部分和槽部分并部分地形成车辆门的外表面的凸缘部分，以及 构造成覆盖凸缘部分的窗框模制件。 凸缘部具有第一构造，其中凸缘部分不被窗框模制件覆盖，并且凸缘部分被窗框模制件覆盖和压缩的第二构造。
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18.发明授权Method of manufacturing semiconductor integrated circuit device comprising a memory cell and a capacitor 失效包括存储单元和电容器的半导体集成电路器件的制造方法公开(公告)号：US06746913B2
公开(公告)日：2004-06-08
申请号：US10083416
申请日：2002-02-27
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31116 , H01L21/31612 , H01L27/0629 , H01L27/10814 , H01L27/10852 , H01L27/10894
摘要： A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.
摘要翻译： 在其上形成有半导体集成电路器件的电容器的氧化硅膜通过等离子体CVD法在450℃至700℃的温度下形成。在该半导体集成电路器件中，由MISFET形成的存储单元 用于数据传送，并且在存储单元形成区域中形成电容器，并且在逻辑电路形成区域中形成构成逻辑电路的n沟道MISFET和ap沟道MISFET。 结果，可以减少从氧化硅膜脱气的量。 因此，构成电容器的下电极的硅膜的表面上的硅晶粒的生长不受脱气的阻碍，能够增加电容。 此外，可以省略在形成氧化硅膜之后除去水分等的步骤，并且可以防止MISFET的性能劣化。
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公开(公告)号：US06183044B2
公开(公告)日：2001-02-06
申请号：US09490062
申请日：2000-01-24
申请人： Toshiro Koyanagi , Koji Hiramatsu , Tsuyoshi Fujiwara , Yoshinobu Sawamoto , Toshiaki Iwasaki , Atsushi Hiroshige , Shunichi Katsumata
发明人： Toshiro Koyanagi , Koji Hiramatsu , Tsuyoshi Fujiwara , Yoshinobu Sawamoto , Toshiaki Iwasaki , Atsushi Hiroshige , Shunichi Katsumata
IPC分类号： B60N228
CPC分类号： B60N2/2821 , B60N2/289
摘要： A child seat is formed of a child seat main portion for holding a child having an engaging member, and a base on which the child seat main portion is detachably mounted. The base has a connecting portion to be connected to a vehicle, and a fixing member to be engageable with the engaging member of the child seat main portion. An engagement releasing member is installed in the base or the child seat main portion for releasing an engagement between the fixing member and the engaging member. Since the base can be connected to the vehicle without the child seat main portion, the child seat can be extremely simply fixed to the vehicle.
摘要翻译： 儿童座椅由用于保持具有接合构件的儿童的儿童座椅主体部分和儿童座椅主体部分可拆卸地安装在其上的基座形成。 基座具有连接到车辆的连接部分和可与儿童座椅主体部分的接合部件接合的固定部件。 接合释放构件安装在基座或儿童座椅主体部分中，用于释放固定构件和接合构件之间的接合。 由于基座可以连接到没有儿童座椅主要部分的车辆，所以儿童座椅可以非常简单地固定在车辆上。
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公开(公告)号：US20120298319A1
公开(公告)日：2012-11-29
申请号：US13575390
申请日：2011-02-01
CPC分类号： D21C9/06 , B01D39/1607 , B01D39/18 , B01D67/0004 , B01D69/10 , B01D71/10 , B01D2239/0613 , B01D2239/0618 , B01D2239/10 , B01D2323/42 , D21H11/18 , D21H15/02 , Y10T428/249921 , Y10T428/298
摘要： The present invention relates to a method of producing a cellulose-fiber flat structure, the method including obtaining a cellulose-fiber flat structure by filtering a fine cellulose-fiber dispersion containing fine cellulose fibers having an average fiber diameter of 4 to 100 nm, using a filter material having a water permeability of not more than 100 ml/m2·s and an initial tensile modulus of 20 MPa or greater. The present invention is able to produce a cellulose-fiber flat structure by efficiently recovering fine cellulose fibers from a dispersion containing fine cellulose fibers having an average fiber diameter at the nano level. The method of producing a cellulose-fiber flat structure can also be applied to a continuous process.
摘要翻译： 纤维素纤维扁平结构体的制造方法技术领域本发明涉及纤维素纤维平坦结构体的制造方法，其特征在于，使用平均纤维直径为4〜100nm的细纤维素纤维的细纤维素纤维分散体， 透水度不大于100ml / m 2·s，初始拉伸弹性模量为20MPa以上的过滤材料。 本发明能够通过从包含平均纤维直径在纳米级的细纤维素纤维的分散体中有效地回收细纤维素纤维而制造纤维素纤维平坦结构。 纤维素纤维平坦结构的制造方法也可以应用于连续工序。
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