公开(公告)号：US20100143980A1

公开(公告)日：2010-06-10

申请号：US12528172

申请日：2008-02-15

Applicant: Kuberan Balagurunathan ,  Ethirajan Manivannan ,  V. Victor Xylophone ,  Vy My Tran ,  Khiem Nguyen

Inventor： Kuberan Balagurunathan ,  Ethirajan Manivannan ,  V. Victor Xylophone ,  Vy My Tran ,  Khiem Nguyen

IPC: C12P19/04 ,  C07H19/056 ,  C07H19/06

CPC classification number: C07H1/00 ,  A61K31/70 ,  C07H19/056

Abstract: The present invention includes a xyloside for use in inducing synthesis of a glycosaminoglycan in a cell, the xyloside having a chemical structure of one of Formula (1), Formula (2), Formula (3), Formula (4), Formula (5), Formula (6), Formula (7), Formula (8), Formula (9), or Formula (10) as shown herein. Also, the present invention includes a method of making a xyloside for use in inducing synthesis of a glycosaminoglycan in a cell, wherein the method is performed with “Click” chemistry. Additionally, the present invention includes a method of administering a xyloside so as to induce synthesis of a glycosaminoglycan in a cell.

Abstract translation: 本发明包括用于诱导细胞中糖胺聚糖合成的木糖苷，具有式（1），式（2），式（3），式（4），式（5）之一的化学结构的木糖苷 ），式（6），式（7），式（8），式（9）或式（10）。 此外，本发明包括制备用于诱导细胞中糖胺聚糖合成的木糖苷的方法，其中所述方法用“点击”化学进行。 此外，本发明包括施用木糖苷以诱导细胞中糖胺聚糖合成的方法。

公开(公告)号：US20080303703A1

公开(公告)日：2008-12-11

申请号：US12133458

申请日：2008-06-05

Applicant: Olafur Josefsson ,  Khiem Nguyen

Inventor： Olafur Josefsson ,  Khiem Nguyen

IPC: H03M3/02

CPC classification number: H03M3/47 ,  H03M3/454 ,  H03M3/456

Abstract: A cross-coupled switched capacitor circuit that has two branches. During a first phase for the first branch, an input voltage is provided that causes charge to move through a resistor and to be placed onto a plate of the capacitor within the branch. An equivalent amount of charge is transferred to an output node. The output node may be a summing node of a sigma-delta modulator. The summing node is one of the inputs to an operational amplifier that is part of the integrator of the sigma-delta modulator. The resistor and the capacitor in the first branch define an RC circuit and corresponding RC time constant. During the first phase, the capacitor does not reach a fully settled voltage for a desired resolution. During the second phase, the capacitor in the first branch of the circuit is set to a defined voltage. The defined voltage may be the settling voltage had the capacitor been allowed to settle during the first phase. The second branch of the switched capacitor feedback circuit operates similar to the first branch, but on opposite phases. By not requiring the voltage to settle during the first phase, power can be conserved, since the integrator of the sigma-delta modulator does not need to operate as fast with respect to movement of charge.

Abstract translation: 具有两个分支的交叉耦合开关电容器电路。 在第一分支的第一阶段期间，提供输入电压，其使电荷移动通过电阻器并且被放置在分支内的电容器的板上。 等量的电荷被传送到输出节点。 输出节点可以是Σ-Δ调制器的求和节点。 求和节点是作为Σ-Δ调制器的积分器一部分的运算放大器的输入之一。 第一分支中的电阻和电容限定了RC电路和相应的RC时间常数。 在第一阶段期间，电容器不能达到完全稳定的电压以达到所需的分辨率。 在第二阶段期间，将电路的第一分支中的电容器设置为限定的电压。 定义的电压可以是在第一阶段允许电容器稳定的稳定电压。 开关电容器反馈电路的第二支路类似于第一分支，但是处于相反的相位。 由于不需要在第一阶段期间稳定电压，所以可以节省功率，因为​​Σ-Δ调制器的积分器不需要相对于电荷的运动来操作得很快。

公开(公告)号：US20050133166A1

公开(公告)日：2005-06-23

申请号：US10782300

申请日：2004-02-18

Applicant: Peter Satitpunwaycha ,  Khiem Nguyen ,  Alfred Mak ,  Kenneth Collins ,  Turgut Sahin

Inventor： Peter Satitpunwaycha ,  Khiem Nguyen ,  Alfred Mak ,  Kenneth Collins ,  Turgut Sahin

IPC: C23C16/458 ,  H01L21/00 ,  H01L21/687 ,  C23F1/00

CPC classification number: H01L21/68735 ,  H01J37/321 ,  H01J2237/2001 ,  H01L21/67069 ,  H01L21/68785

Abstract: The present invention generally provides an improved pedestal for supporting a substrate. The pedestal has greatest application during a plasma etching process, such as for a quartz photomask, or “reticle.” The pedestal defines a body, and a substrate support base along an upper surface of the body. The substrate support base has an outer edge, and an intermediate substrate support ridge for receiving and supporting the substrate. At least a portion of the substrate support base outside of the intermediate substrate support ridge is fabricated from a dielectric material. The purpose is to couple greater RF power through the reticle in order to enhance the plasma etching process.

Abstract translation: 本发明通常提供一种用于支撑基底的改进的基座。 基座在等离子体蚀刻过程中具有最大的应用，例如石英光掩模或“掩模版”。 基座限定主体，以及沿着主体的上表面的基板支撑基座。 基板支撑基座具有外边缘，以及用于接收和支撑基板的中间基板支撑脊。 中间基板支撑脊外侧的基板支撑基座的至少一部分由电介质材料制成。 目的是通过光罩耦合更大的RF功率，以增强等离子体蚀刻工艺。

公开(公告)号：US20120062726A1

公开(公告)日：2012-03-15

申请号：US13302308

申请日：2011-11-22

Applicant: Robert L. Hsieh ,  Khiem Nguyen ,  Warren W. Flack ,  Andrew M. Hawryluk

Inventor： Robert L. Hsieh ,  Khiem Nguyen ,  Warren W. Flack ,  Andrew M. Hawryluk

IPC: H04N7/18

CPC classification number: G03F9/7084 ,  G03F9/7065 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7088 ,  H01L33/22

Abstract: An alignment system for aligning a wafer when lithographically fabricating LEDs having an LED wavelength λLED is disclosed. The system includes the wafer. The wafer has a roughened alignment mark with a root-mean-square (RMS) surface roughness σS. The system has a lens configured to superimpose an image of the reticle alignment mark with an image of the roughened alignment mark. The roughened alignment marked image is formed with alignment light having a wavelength λA that is in the range from about 2σS to about 8σS. An image sensor detects the superimposed image. An image processing unit processes the detected superimposed image to measure an alignment offset between the wafer and the reticle.

Abstract translation: 公开了一种用于在光刻制造具有LED波长λLED的LED的晶片时对准晶片的对准系统。 该系统包括晶片。 晶片具有粗糙的对准标记，均方根（RMS）表面粗糙度S。 该系统具有配置为用掩模版对准标记的图像叠加掩模版对准标记的图像的透镜。 粗糙的对准标记图像由波长λA为约2＆Sgr; S至约8＆Sgr; S的对准光形成。 图像传感器检测叠加图像。 图像处理单元处理检测到的叠加图像以测量晶片和标线片之间的对准偏移。

公开(公告)号：US07846848B2

公开(公告)日：2010-12-07

申请号：US11532195

申请日：2006-09-15

Applicant: Richard Lewington ,  Corey Collard ,  Scott Anderson ,  Khiem Nguyen

Inventor： Richard Lewington ,  Corey Collard ,  Scott Anderson ,  Khiem Nguyen

IPC: H01L21/302

CPC classification number: G03F1/30 ,  H01L21/31116 ,  H01L21/67742

Abstract: The embodiments of the invention relate to a method and apparatus for measuring the etch depth in a semiconductor photomask processing system. In one embodiment, a method for etching a substrate includes etching a transparent substrate in an etch chamber coupled to a vacuum transfer chamber of a processing system, transferring the transparent substrate to a measurement cell coupled to the processing system, and measuring at least one of etch depth or critical dimension using a measurement tool in the measurement cell.

Abstract translation: 本发明的实施例涉及一种用于测量半导体光掩模处理系统中的蚀刻深度的方法和装置。 在一个实施例中，用于蚀刻衬底的方法包括在与处理系统的真空传送室耦合的蚀刻室中蚀刻透明衬底，将透明衬底转移到耦合到处理系统的测量单元，以及测量至少一个 蚀刻深度或临界尺寸，使用测量单元中的测量工具。

公开(公告)号：US07683815B2

公开(公告)日：2010-03-23

申请号：US12133458

申请日：2008-06-05

Applicant: Olafur Josefsson ,  Khiem Nguyen

Inventor： Olafur Josefsson ,  Khiem Nguyen

IPC: H03M3/00

CPC classification number: H03M3/47 ,  H03M3/454 ,  H03M3/456

Abstract: A cross-coupled switched capacitor circuit that has two branches. During a first phase for the first branch, an input voltage is provided that causes charge to move through a resistor and to be placed onto a plate of the capacitor within the branch. An equivalent amount of charge is transferred to an output node. The output node may be a summing node of a sigma-delta modulator. The summing node is one of the inputs to an operational amplifier that is part of the integrator of the sigma-delta modulator. The resistor and the capacitor in the first branch define an RC circuit and corresponding RC time constant. During the first phase, the capacitor does not reach a fully settled voltage for a desired resolution. During the second phase, the capacitor in the first branch of the circuit is set to a defined voltage. The defined voltage may be the settling voltage had the capacitor been allowed to settle during the first phase. The second branch of the switched capacitor feedback circuit operates similar to the first branch, but on opposite phases. By not requiring the voltage to settle during the first phase, power can be conserved, since the integrator of the sigma-delta modulator does not need to operate as fast with respect to movement of charge.

Abstract translation: 具有两个分支的交叉耦合开关电容器电路。 在第一分支的第一阶段期间，提供输入电压，其使电荷移动通过电阻器并且被放置在分支内的电容器的板上。 等量的电荷被传送到输出节点。 输出节点可以是Σ-Δ调制器的求和节点。 求和节点是作为Σ-Δ调制器的积分器一部分的运算放大器的输入之一。 第一分支中的电阻和电容限定了RC电路和相应的RC时间常数。 在第一阶段期间，电容器不能达到完全稳定的电压以达到所需的分辨率。 在第二阶段期间，将电路的第一分支中的电容器设置为限定的电压。 定义的电压可以是在第一阶段允许电容器稳定的稳定电压。 开关电容器反馈电路的第二支路类似于第一分支，但是处于相反的相位。 由于不需要在第一阶段期间稳定电压，所以可以节省功率，因为​​Σ-Δ调制器的积分器不需要相对于电荷的运动来操作得很快。

公开(公告)号：US07423573B2

公开(公告)日：2008-09-09

申请号：US11616468

申请日：2006-12-27

Applicant: Paul A. Baginski ,  Robert Adams ,  Khiem Nguyen

Inventor： Paul A. Baginski ,  Robert Adams ,  Khiem Nguyen

IPC: H03M1/66

CPC classification number: H03M3/502 ,  H03H19/004

Abstract: A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.

Abstract translation: 数模转换器（DAC）包括第一连续时段，其接收与数字信号相关联的输入信号，并对输入信号执行连续时间数模转换操作。 第一连续时段输出第一输出信号。 第二开关电容器级接收第一输出信号并执行第一输出信号的开关电容滤波。 第二开关电容器级输出发送到低通滤波器的第二输出信号以形成与数字信号相关联的连续模拟信号。

公开(公告)号：US20070124217A1

公开(公告)日：2007-05-31

申请号：US11283560

申请日：2005-11-17

Applicant: Marsha Terry ,  Michael Scalora ,  Jason Hunter ,  Donna Leacock ,  Jeffrey DeMoss ,  Walter Holladay ,  Khiem Nguyen ,  David Duncan

Inventor： Marsha Terry ,  Michael Scalora ,  Jason Hunter ,  Donna Leacock ,  Jeffrey DeMoss ,  Walter Holladay ,  Khiem Nguyen ,  David Duncan

IPC: G06Q10/00

CPC classification number: G06Q10/00 ,  G06Q10/087

Abstract: Systems and methods provide quantity availability information for inventory items via a user interface. The user customizes a quantity available definition, from which the system calculates quantity available for various inventory items and dynamically updates the calculation as a result of changes to inventory classes making up the definition. Using access points within inventory tracking software, the system displays quantity available information to the user via various display formats.

Abstract translation: 系统和方法通过用户界面提供库存物品的数量可用性信息。 用户自定义数量可用定义，系统可以从中计算可用于各种库存项目的数量，并由于更改构成定义的库存类别而动态更新计算。 在库存跟踪软件中使用接入点，系统通过各种显示格式向用户显示可用数量的信息。

公开(公告)号：US20070007660A1

公开(公告)日：2007-01-11

申请号：US11530676

申请日：2006-09-11

Applicant: Khiem Nguyen ,  Peter Satitpunwaycha ,  Alfred Mak

Inventor： Khiem Nguyen ,  Peter Satitpunwaycha ,  Alfred Mak

IPC: H01L23/52

CPC classification number: H01L21/68707 ,  H01J37/321 ,  H01J37/32623 ,  H01L21/68735

Abstract: Method and apparatus for supporting and transferring a substrate in a semiconductor wafer processing system are provided. In one aspect, an apparatus is provided for supporting a substrate comprising a cover ring comprising a base having a bore disposed therethough, the base having an upper surface and one or more raised surfaces disposed adjacent the bore, wherein the raised surface comprise one or more first substrate support members disposed adjacent an edge of the bore and a capture ring disposed on the cover ring, the capture ring comprising a semi-circular annular ring having an inner perimeter corresponding to the bore of the cover ring and one or more second substrate support members disposed on the inner perimeter and adapted to receive a substrate, wherein the capture ring is adapted to mate with the cover ring and form one contiguous raised surface on the cover ring.

Abstract translation: 提供了用于在半导体晶片处理系统中支撑和转移衬底的方法和装置。 在一个方面，提供了一种用于支撑衬底的装置，其包括盖环，该盖环包括其上设置有孔的基部，所述基部具有上表面和邻近所述孔布置的一个或多个凸起表面，其中所述凸起表面包括一个或多个 第一衬底支撑构件邻近孔的边缘设置，并且捕获环设置在覆盖环上，捕获环包括半圆环形环，其具有对应于盖环的孔的内周边和一个或多个第二衬底支撑件 设置在内周上并适于接收基底的构件，其中捕获环适于与盖环配合并在盖环上形成一个连续的凸起表面。

公开(公告)号：US07009541B1

公开(公告)日：2006-03-07

申请号：US10970213

申请日：2004-10-21

Applicant: Khiem Nguyen

Inventor： Khiem Nguyen

IPC: H03M3/00

CPC classification number: H03M3/356 ,  H03M3/454 ,  H03M3/464

Abstract: A novel circuit is used to monitor the common-mode voltage at the summing junctions of the first integrator in a continuous-time ΣΔ ADC, wherein the circuit produces a control voltage which adjusts the quiescent current of the feedback DAC to compensate for any common-mode offset current. Since the adjustment takes place within the feedback DAC, there is no extra noise added to the differential signal path. The implementation provides for no degradation to the SNR of the converter.

Abstract translation: 一个新颖的电路用于监视连续时间SigmaDelta ADC中第一个积分器的求和点处的共模电压，其中该电路产生一个控制电压，该电压调节反馈DAC的静态电流以补偿任何共模电压， 模式偏移电流。 由于调节发生在反馈DAC内，因此不会对差分信号路径加上额外的噪声。 该实施方案不会降低转换器的SNR。