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67 条记录 (耗时 0.035 秒)

    DLL lock scheme with multiple phase detection
    17.
    发明授权
    DLL lock scheme with multiple phase detection 有权
    具有多相检测的DLL锁定方案

    公开(公告)号：US06388482B1

    公开(公告)日：2002-05-14

    申请号：US09598350

    申请日：2000-06-21

    申请人： Josef Schnell ,  Oliver Kiehl

    发明人： Josef Schnell ,  Oliver Kiehl

    IPC分类号： H03L706

    CPC分类号： H03L7/0814 ,  H03L7/087

    摘要： A delay lock loop, in accordance with the present invention, includes a plurality of phase detectors each receiving a first clock signal and a second clock signal. Each phase detector includes a specified delay range for detecting phase differences between the first and second clock signals in that range. A delay line includes an input and an output. The first clock signal is received at the input, and the second clock signal includes a delayed first clock signal. An amount of delay is applied to the first clock signal, which is adjusted in the delay line in accordance with control signals of the phase detectors.

    摘要翻译： 根据本发明的延迟锁定环包括多个相位检测器，每个相位检测器接收第一时钟信号和第二时钟信号。 每个相位检测器包括用于检测在该范围内的第一和第二时钟信号之间的相位差的规定的延迟范围。 延迟线包括输入和输出。 在输入端接收第一时钟信号，第二时钟信号包括延迟的第一时钟信号。 根据相位检测器的控制信号，对延迟线进行调整的第一时钟信号施加延迟量。

    Data transmission system with reduced power consumption
    18.
    发明授权
    Data transmission system with reduced power consumption 有权
    数据传输系统功耗降低

    公开(公告)号：US07321628B2

    公开(公告)日：2008-01-22

    申请号：US10674859

    申请日：2003-09-30

    申请人： Oliver Kiehl

    发明人： Oliver Kiehl

    IPC分类号： H04L27/00

    CPC分类号： H04L25/4915

    摘要： System and method for reducing power consumption and noise in a transmission system with an asymmetrically terminated transmission line. A preferred embodiment comprises encoding data words to reduce the number of times a given state appears in a code word. The preferred embodiment comprises counting the number of times a given state appears in a data word. If the count is greater than half of the total number of bits in the data word, then the data word is inverted and a weight bit can be set to the given state. If the count is less than (or equal to) half of the total number of bits, then the data word may be unchanged and the weight bit can be set to the inverse of the given state. The code word can be generated by appending the weight bit to the data word.

    摘要翻译： 具有不对称端接传输线的传输系统中降低功耗和噪声的系统和方法。 优选实施例包括编码数据字以减少给定状态在码字中出现的次数。 优选实施例包括对给定状态在数据字中出现的次数进行计数。 如果计数大于数据字中总位数的一半，则数据字被反转，并且可以将权重位设置为给定状态。 如果计数小于（或等于）总位数的一半，则数据字可以不变，并且权重位可以被设置为给定状态的倒数。 可以通过将权重位附加到数据字来生成代码字。

    Memory device and method using a sense amplifier as a cache
    19.
    发明授权
    Memory device and method using a sense amplifier as a cache 有权
    使用读出放大器作为缓存的存储器件和方法

    公开(公告)号：US07215595B2

    公开(公告)日：2007-05-08

    申请号：US10967899

    申请日：2004-10-18

    申请人： Oliver Kiehl

    发明人： Oliver Kiehl

    IPC分类号： G11C8/18

    CPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005

    摘要： A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.

    摘要翻译： 存储器件包括一对补充位线，包括第一位线和第二位线。 位线预充电块耦合在第一位线和第二位线之间。 读出放大器耦合到第一位线和第二位线，读出放大器预充电块耦合到读出放大器。 读出放大器预充电块可以独立于位线预充电块来激活。 隔离块耦合在一对互补位线和一侧的位线预充电块和另一侧的读出放大器和读出放大器预充电块之间。

    Semiconductor package and method
    20.
    发明授权
    Semiconductor package and method 失效
    半导体封装及方法

    公开(公告)号：US06730989B1

    公开(公告)日：2004-05-04

    申请号：US09596130

    申请日：2000-06-16

    申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    IPC分类号： H01L23544

    CPC分类号： H01L23/5382 ,  H01L23/50 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

    摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。