公开(公告)号：US4731761A

公开(公告)日：1988-03-15

申请号：US915679

申请日：1986-10-06

申请人： Toshifumi Kobayashi

发明人： Toshifumi Kobayashi

IPC分类号： G11C11/408 ,  G11C8/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/413 ,  G11C13/00

CPC分类号： G11C8/10 ,  G11C8/12

摘要： A dynamic RAM with static column function comprising a predecoder for predecoding both the row address and the column address to output intermediate signals, a row decoder composed of NOR circuits for selecting one row in response to said intermediate signals, a column decoder composed of NAND circuits for selecting one column in response to said intermediate signals, and a logic inversion circuit for matching the logics for the intermediate signal between the row decoder and the column decoder.

摘要翻译： 一种具有静态列功能的动态RAM，包括用于对行地址和列地址进行预解码以输出中间信号的预解码器，由NOR电路组成的行解码器，用于响应于所述中间信号选择一行;列解码器，其由NAND电路 用于响应于所述中间信号选择一列;以及逻辑反相电路，用于匹配行解码器和列解码器之间的中间信号的逻辑。

公开(公告)号：US06777981B2

公开(公告)日：2004-08-17

申请号：US10267855

申请日：2002-10-10

申请人： Toshifumi Kobayashi

发明人： Toshifumi Kobayashi

IPC分类号： H03L500

CPC分类号： H03K3/356165 ,  H03K3/356113

摘要： A level shifting circuit includes a charging means consisting of a charging regulator circuit which charges a second node to a logic “H” by setting a second switching circuit to an ON state and thereafter brings back the second switching circuit to an OFF state when a first node is changed from a logic “H” to a logic “L” by a change of an input signal, and charges the first node to the logic “H” by setting a first switching circuit to the ON state and thereafter brings back the first switching circuit to the OFF state when the second node is changed from the logic “H” to the logic “L” by the change of the input signal.

摘要翻译： 电平移位电路包括充电装置，其由充电调节器电路组成，该充电调节器电路通过将第二开关电路设置为导通状态而将第二节点充电至逻辑“H”，并且此后将第二开关电路恢复为截止状态， 节点通过输入信号的改变从逻辑“H”改变为逻辑“L”，并且通过将第一开关电路设置为导通状态将第一节点充电为逻辑“H”，并且此后将第一 当第二节点通过输入信号的改变从逻辑“H”改变为逻辑“L”时，切换电路处于断开状态。

公开(公告)号：US06767631B2

公开(公告)日：2004-07-27

申请号：US10053769

申请日：2002-01-22

申请人： Manabu Ono ,  Toshifumi Kobayashi

发明人： Manabu Ono ,  Toshifumi Kobayashi

IPC分类号： B32B2730

CPC分类号： C09J4/00 ,  C09J7/385 ,  Y10T428/28 ,  Y10T428/2852 ,  Y10T428/2887 ,  Y10T428/2891 ,  C08F220/18 ,  C08F220/36

摘要： The present invention aims to provide an adhesive composition showing high adhesion and cohesion as well as good heat resistance. Adhesive compositions of the present invention include an imide (meth)acrylate, a monomer having a glass transition temperature of −50° C. or less when it is homopolymerized, and a photoinitiator, wherein the content of the imide (meth)acrylate is 1-20 parts by weight per 100 parts by weight of the monomer.

摘要翻译： 本发明的目的在于提供一种显示高粘合性和内聚性以及良好的耐热性的粘合剂组合物。 本发明的粘合剂组合物包括酰亚胺（甲基）丙烯酸酯，当其均聚时玻璃化转变温度为-50℃以下的单体和光引发剂，其中酰亚胺（甲基）丙烯酸酯的含量为1 相对于100重量份单体为-20重量份。

公开(公告)号：US4965767A

公开(公告)日：1990-10-23

申请号：US380428

申请日：1989-07-17

申请人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

发明人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.

摘要翻译： 公开了仅由四个NMOS晶体管组成的相关存储器的存储单元电路。 电路的每个存储单元连接两个位线，字线，用于命令一致检测的匹配设置线和用于传送检测结果的匹配线。 数据信号以每个晶体管3的栅极容量存储。这种简化的存储单元电路有助于关联存储器的更高的集成。

公开(公告)号：US4901282A

公开(公告)日：1990-02-13

申请号：US328814

申请日：1989-03-24

申请人： Toshifumi Kobayashi

发明人： Toshifumi Kobayashi

IPC分类号： G11C7/22 ,  G11C11/406

CPC分类号： G11C7/22 ,  G11C11/406

摘要： In a static column dynamic random access memory device in which memory operations including refresh operation are initiated responsive to a row address strobe signal, and the refresh operation for amplification and rewriting of information of the selected memory cell is not interrupted until its completion once it is started by the application of the row address strobe signal even if the row address strobe signal is thereafter removed;a timing circuit provides clocks for controlling the row circuits and the column circuit to cause termination of the memory operations if the row address strobe signal has been removed before the end of the refresh operation, and to cause continuation of the read/write memory operations if the row address strobe signal is still applied at the end of the refresh operation.

摘要翻译： 在静态列动态随机存取存储器件中，其中响应于行地址选通信号启动包括刷新操作的存储器操作，并且用于放大和重写所选择的存储器单元的信息的刷新操作直到其完成之后才被中断 即使行地址选通信号被去除，也通过施加行地址选通信号而开始; 定时电路提供用于控制行电路和列电路的时钟，以便在刷新操作结束之前行行地址选通信号被去除并导致读/写存储器操作的继续，如果 在刷新操作结束时仍然应用行地址选通信号。

公开(公告)号：US5130945A

公开(公告)日：1992-07-14

申请号：US551268

申请日：1990-07-12

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Masaaki Mihara

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04 ,  G11C15/043

摘要： Each match line is connected to a plurality of CAM cells constituting a CAM array. The respective CAM cells store data applied through a bit line and an inverted-bit line in its data storage portion when selected by a word line. The stored data are applied to a data comparison portion to be compared with retrieval data applied through the bit line and the inverted-bit line, thereby detecting match or mismatch therebetween. A comparison result of the data comparison portion is first stored in a capacitance element in the form of charge. In order to prevent escape of the information stored in the capacitance element, a blocking means blocks a part of a charge and discharge path for the capacitance element. A charge transfer means provided between the capacitance element and the match line transfers a certain amount of charge from either one to the other when information of mismatch is stored in the capacitance element. This causes fluctuation of charge potential on the match line. The fluctuation of potential on the match line depends on the number of mismatched CAM cells out of a plurality of CAM cells connected to the match line. Therefore, detection of potential on the match line permits detecting the number of mismatched CAM cells.

摘要翻译： 每个匹配线连接到构成CAM阵列的多个CAM单元。 当通过字线选择时，相应的CAM单元存储在其数据存储部分中通过位线和反相位线施加的数据。 将存储的数据应用于数据比较部分，以与通过位线和反向位线施加的检索数据进行比较，从而检测它们之间的匹配或失配。 数据比较部分的比较结果首先以电荷的形式存储在电容元件中。 为了防止存储在电容元件中的信息的逸出，阻塞装置阻挡电容元件的充电和放电路径的一部分。 当在电容元件中存储不匹配的信息时，设置在电容元件和匹配线之间的电荷转移装置将一定量的电荷从两者之一传递到另一个。 这导致匹配线上的电荷电位波动。 匹配线上的电位波动取决于连接到匹配线的多个CAM单元中不匹配的CAM单元的数量。 因此，匹配线上的电位检测允许检测不匹配的CAM单元的数量。

公开(公告)号：US4924220A

公开(公告)日：1990-05-08

申请号：US286922

申请日：1988-11-18

申请人： Masaaki Mihara ,  Toshifumi Kobayashi

发明人： Masaaki Mihara ,  Toshifumi Kobayashi

IPC分类号： G06F15/16 ,  G06F13/14 ,  G06F13/362 ,  G06F13/364 ,  G06F15/177

CPC分类号： G06F13/14 ,  G06F13/364

摘要： An arbiter circuit is disclosed for processing competing requests for access to a shared resource made simultaneously by two subsystems in a multi-processor system. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates, and functions to block the passage of a subsequent request signal from one subsystem to the SR flip-flop during a predetermined time interval after a request signal from the other subsystem has been supplied to the flip-flop. A result is that the both inputs of the SR flip-flop are not shifted up from the low levels to the high levels at the same time by the simultaneous generation of request signals from both subsystems, thereby eliminating any possibility of the output from the flip-flop floating at an intermediate level between the high and low level.

摘要翻译： 公开了一种仲裁器电路，用于处理在多处理器系统中由两个子系统同时进行的对共享资源的访问的竞争请求。 仲裁器电路包括由一对NAND门组成的SR触发器，并且在来自另一个子系统的请求信号之后的预定时间间隔期间阻止后续请求信号从一个子系统到SR触发器的通过 已被提供给触发器。 结果是，通过同时生成来自两个子系统的请求信号，SR触发器的两个输入都不会从低电平向上移动到高电平，从而消除了从翻转的输出的任何可能性 - 浮动在高低位之间的中间水平。

公开(公告)号：US4818904A

公开(公告)日：1989-04-04

申请号：US143398

申请日：1988-01-13

申请人： Toshifumi Kobayashi

发明人： Toshifumi Kobayashi

IPC分类号： G06F1/24 ,  H03K17/22 ,  H03K17/60

CPC分类号： H03K17/223

摘要： A power on reset pulse generating circuit, which comprises a flip-flop coupled through capacitors to an applied supply voltage to be resettable thereby, a time constant circuit including an array of diode connecting MOS transistors and a capacitor coupled to reset the flip-flop in response to a fast rise time of an applied supply voltage, and another MOS transistor connected to detect a level of a voltage at the output terminal to reset the flip-flop in response to a slow rise time of the applied supply voltage.

摘要翻译： 一种上电复位脉冲发生电路，其包括通过电容器耦合到可由其复位的施加电源电压的触发器，时间常数电路，包括二极管连接MOS晶体管阵列和耦合以复位触发器的电容器 响应于所施加的电源电压的快速上升时间，以及另一个MOS晶体管，其被连接以响应于所施加的电源电压的缓慢上升时间来检测输出端子处的电压的电平以复位触发器。