公开(公告)号：US09312478B2

公开(公告)日：2016-04-12

申请号：US13589708

申请日：2012-08-20

申请人： Hak-sun Lee ,  Tokashiki Ken ,  Myeong-cheol Kim ,  Hyung-joon Kwon ,  Sang-min Lee ,  Woo-cheol Lee ,  Myung-hoon Jung

发明人： Hak-sun Lee ,  Tokashiki Ken ,  Myeong-cheol Kim ,  Hyung-joon Kwon ,  Sang-min Lee ,  Woo-cheol Lee ,  Myung-hoon Jung

IPC分类号： H01L21/3065 ,  H01L43/12 ,  B81C1/00 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/31 ,  H01L27/22

CPC分类号： H01L43/12 ,  B81C1/00531 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3163 ,  H01L21/3065 ,  H01L27/228 ,  Y10T428/24479

摘要： Magnetic devices, and methods of manufacturing the same, include a stack structure including at least one magnetic layer, etched using an etching gas including at least 70 volume percent of a hydrogen-containing gas and at least 2 volume percent of CO gas.

摘要翻译： 磁性器件及其制造方法包括使用包括至少70体积％的含氢气体和至少2体积％的CO气体的蚀刻气体蚀刻的至少一个磁性层的堆叠结构。

公开(公告)号：US09054051B2

公开(公告)日：2015-06-09

申请号：US13473091

申请日：2012-05-16

申请人： Soo-yeon Jeong ,  In-ho Kim ,  Hyung-yong Kim ,  Myeong-cheol Kim

发明人： Soo-yeon Jeong ,  In-ho Kim ,  Hyung-yong Kim ,  Myeong-cheol Kim

IPC分类号： H01L21/311 ,  H01L27/102 ,  H01L49/02 ,  H01L45/00 ,  H01L27/24 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L21/76898 ,  H01L27/1021 ,  H01L27/2409 ,  H01L28/91 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

摘要： In a method of fabricating a semiconductor device, a target layer and a first material layer are sequentially formed on a substrate. A plurality of second material layer patterns are formed on the first material layer, the second material layer patterns extending in a first horizontal direction. A plurality of hardmask patterns extending in a second horizontal direction are formed on the plurality of second material layer patterns and the first material layer, wherein the second horizontal direction is different from the first horizontal direction. A first material layer pattern is formed by etching the first material layer using the plurality of hardmask patterns and the plurality of second material layer patterns as etch masks. A target layer pattern with a plurality of holes is formed by etching the target layer using the first material layer pattern as an etch mask.

摘要翻译： 在制造半导体器件的方法中，目标层和第一材料层依次形成在衬底上。 在第一材料层上形成多个第二材料层图案，第二材料层图案沿第一水平方向延伸。 在多个第二材料层图案和第一材料层上形成有沿第二水平方向延伸的多个硬掩模图案，其中第二水平方向与第一水平方向不同。 通过使用多个硬掩模图案和多个第二材料层图案作为蚀刻掩模蚀刻第一材料层来形成第一材料层图案。 通过使用第一材料层图案作为蚀刻掩模蚀刻目标层来形成具有多个孔的目标层图案。

公开(公告)号：US09048192B2

公开(公告)日：2015-06-02

申请号：US13493146

申请日：2012-06-11

申请人： Dong-kwon Kim ,  Ki-il Kim ,  Ah-young Cheon ,  Myeong-cheol Kim ,  Yong-jin Kim

发明人： Dong-kwon Kim ,  Ki-il Kim ,  Ah-young Cheon ,  Myeong-cheol Kim ,  Yong-jin Kim

IPC分类号： H01L21/00 ,  H01L21/3065 ,  H01L21/308

CPC分类号： H01L23/5283 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/32139 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.

摘要翻译： 形成图案的方法包括在基板上形成掩模图案; 通过深反应离子蚀刻（DRIE）蚀刻衬底并通过使用掩模图案作为蚀刻掩模; 部分地去除所述掩模图案以暴露所述基板的上表面的一部分; 并蚀刻衬底的上表面的暴露部分。 在该方法中，当由DRIE形成图案时，图案的上部不突出或几乎不突出，并且图案的侧壁的扇形光滑，因此可以容易地在保护层的表面上形成共形材料层 模式。

公开(公告)号：US06385020B1

公开(公告)日：2002-05-07

申请号：US09487740

申请日：2000-01-19

申请人： Hyun-bo Shin ,  Myeong-cheol Kim ,  Jin-won Kim ,  Ki-hyun Hwang ,  Jae-young Park ,  Bon-young Koo

发明人： Hyun-bo Shin ,  Myeong-cheol Kim ,  Jin-won Kim ,  Ki-hyun Hwang ,  Jae-young Park ,  Bon-young Koo

IPC分类号： H02H700

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84

摘要： A hemispherical grain (HSG) capacitor having HSGs on at least a part of the surface of capacitor lower electrodes, and a method of forming the same. In the capacitor, lower electrodes are formed of at least two amorphous silicon layers including an amorphous silicon layer doped with a high concentration of impurities and an amorphous silicon layer doped with a low concentration of impurities, and HSGs are formed, wherein the size of the hemispherical grains can be adjusted such that the size of HSGs formed on the inner surface of a U-shaped lower electrode or on the top of a stacked lower electrode is larger than that of HSGs formed on the outer surface of the U-shaped lower electrode or on the sidews of the stacked lower electrode. Thus, bridging between neighboring lower electrodes can be avoided by appropriately adjusting the size of HSGs, resulting in uniform capacitance wafer-to-wafer and within a wafer. The mechanical strength of the U-shaped lower electrode can also be enhanced.

摘要翻译： 在电容器下电极的表面的至少一部分上具有HSG的半球状晶粒（HSG）电容器及其形成方法。 在电容器中，下电极由至少两个非晶硅层形成，包括掺杂有高浓度杂质的非晶硅层和掺杂有低浓度杂质的非晶硅层，形成HSG， 可以调节半球形颗粒，使得形成在U形下电极的内表面上或堆叠的下电极的顶部上的HSG的尺寸大于形成在U形下电极的外表面上的HSG的尺寸 或在堆叠的下电极的侧面上。 因此，可以通过适当地调节HSG的尺寸来避免相邻的下部电极之间的桥接，导致晶片到晶片和晶片内的均匀电容。 也可以提高U形下电极的机械强度。

公开(公告)号：US09508727B2

公开(公告)日：2016-11-29

申请号：US14853442

申请日：2015-09-14

申请人： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

发明人： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L27/02

CPC分类号： H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

摘要： A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

摘要翻译： 一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极 线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。

公开(公告)号：US20150262839A1

公开(公告)日：2015-09-17

申请号：US14723652

申请日：2015-05-28

申请人： Dong-kwon Kim ,  Ki-il Kim ,  Ah-young Cheon ,  Myeong-cheol Kim ,  Yong-jin Kim

发明人： Dong-kwon Kim ,  Ki-il Kim ,  Ah-young Cheon ,  Myeong-cheol Kim ,  Yong-jin Kim

IPC分类号： H01L21/3213 ,  H01L21/3065

CPC分类号： H01L23/5283 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/32139 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.

摘要翻译： 形成图案的方法包括在基板上形成掩模图案; 通过深反应离子蚀刻（DRIE）蚀刻衬底并通过使用掩模图案作为蚀刻掩模; 部分地去除所述掩模图案以暴露所述基板的上表面的一部分; 并蚀刻衬底的上表面的暴露部分。 在该方法中，当由DRIE形成图案时，图案的上部不突出或几乎不突出，并且图案的侧壁的扇形光滑，因此可以容易地在保护层的表面上形成保形材料层 模式。

公开(公告)号：US08735248B2

公开(公告)日：2014-05-27

申请号：US13475329

申请日：2012-05-18

申请人： Jin-wook Lee ,  Myeong-cheol Kim ,  Heung-sik Park ,  Sang-min Lee ,  Hyun-ho Jung

发明人： Jin-wook Lee ,  Myeong-cheol Kim ,  Heung-sik Park ,  Sang-min Lee ,  Hyun-ho Jung

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L29/78

CPC分类号： H01L29/66795

摘要： A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having a protruding channel region, forming a gate insulation layer surrounding the protruding channel region, forming a sacrificial layer having an etch selectivity varying in a thickness direction of the sacrificial layer, on the gate insulation layer, and performing a gate-last process to form a gate electrode on the gate insulation layer in place of the sacrificial layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有突出沟道区的衬底，形成围绕突出沟道区的栅极绝缘层，在栅绝缘层上形成具有沿牺牲层的厚度方向变化的蚀刻选择性的牺牲层，并执行 栅极最后工艺，以在栅极绝缘层上形成栅电极来代替牺牲层。

公开(公告)号：US08637407B2

公开(公告)日：2014-01-28

申请号：US13242504

申请日：2011-09-23

申请人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

发明人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： G11C16/0483 ,  G11C5/06 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

公开(公告)号：US20120302034A1

公开(公告)日：2012-11-29

申请号：US13475329

申请日：2012-05-18

申请人： Jin-wook Lee ,  Myeong-cheol Kim ,  Heung-sik Park ,  Sang-min Lee ,  Hyun-ho Jung

发明人： Jin-wook Lee ,  Myeong-cheol Kim ,  Heung-sik Park ,  Sang-min Lee ,  Hyun-ho Jung

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/66795

摘要： A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having a protruding channel region, forming a gate insulation layer surrounding the protruding channel region, forming a sacrificial layer having an etch selectivity varying in a thickness direction of the sacrificial layer, on the gate insulation layer, and performing a gate-last process to form a gate electrode on the gate insulation layer in place of the sacrificial layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有突出沟道区的衬底，形成围绕突出沟道区的栅极绝缘层，在栅绝缘层上形成具有沿牺牲层的厚度方向变化的蚀刻选择性的牺牲层，并执行 栅极最后工艺，以在栅极绝缘层上形成栅电极来代替牺牲层。

公开(公告)号：US08263487B2

公开(公告)日：2012-09-11

申请号：US12655344

申请日：2009-12-29

申请人： Dong-ki Yoon ,  Shi-yong Yi ,  Seong-woon Choi ,  Seok-hwan Oh ,  Kwang-sub Yoon ,  Myeong-cheol Kim ,  Young-ju Park

发明人： Dong-ki Yoon ,  Shi-yong Yi ,  Seong-woon Choi ,  Seok-hwan Oh ,  Kwang-sub Yoon ,  Myeong-cheol Kim ,  Young-ju Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/115 ,  H01L27/11517

摘要： A method of forming fine patterns of a semiconductor device by using carbon (C)-containing films includes forming an etching target film on a substrate including first and second regions; forming a plurality of first C-containing film patterns on the etching target film in the first region; forming a buffer layer which covers top and side surfaces of the plurality of first C-containing film patterns; forming a second C-containing film; removing the second C-containing film in the second region; exposing the plurality of first C-containing film patterns by removing a portion of the buffer layer in the first and second regions; and etching the etching target film by using the plurality of first C-containing film patterns, and portions of the second C-containing film which remain in the first region, as an etching mask.

摘要翻译： 通过使用含碳（C）的膜来形成半导体器件的精细图案的方法包括在包括第一和第二区域的衬底上形成蚀刻靶膜; 在所述第一区域中的所述蚀刻目标膜上形成多个第一含C膜的图案; 形成覆盖所述多个第一含C膜图案的顶表面和侧表面的缓冲层; 形成第二含C膜; 去除第二区域中的第二含C膜; 通过去除第一和第二区域中的缓冲层的一部分来暴露多个第一含C膜的图案; 并且通过使用多个第一含C膜膜图案和残留在第一区域中的第二含C膜的部分来蚀刻蚀刻目标膜作为蚀刻掩模。