公开(公告)号：US20160358784A1

公开(公告)日：2016-12-08

申请号：US15237521

申请日：2016-08-15

Applicant: Lam Research Corporation

Inventor： Eric A. Hudson ,  Andrew D. Bailey, III ,  Rajinder Dhindsa

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/67 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01J37/32449 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/32357 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/67069

Abstract: Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.

公开(公告)号：US11594400B2

公开(公告)日：2023-02-28

申请号：US16845723

申请日：2020-04-10

Applicant: Lam Research Corporation

Inventor： Ryan Bise ,  Rajinder Dhindsa ,  Alexei Marakhtanov ,  Lumin Li ,  Sang Ki Nam ,  Jim Rogers ,  Eric Hudson ,  Gerardo Delgadino ,  Andrew D. Bailey, III ,  Mike Kellogg ,  Anthony de la Llera ,  Darrell Ehrlich

IPC: H01J37/32 ,  H01L21/67

Abstract: A plasma processing system includes a plasma chamber having a substrate support, and a multi-zone gas injection upper electrode disposed opposite the substrate support. An inner plasma region is defined between the upper electrode and the substrate support. The multi-zone gas injection upper electrode has a plurality of concentric gas injection zones. A confinement structure, which surrounds the inner plasma region, has an upper horizontal wall that interfaces with the outer electrode of the upper electrode. The confinement structure has a lower horizontal wall that interfaces with the substrate support, and includes a perforated confinement ring and a vertical wall that extends from the upper horizontal wall to the lower horizontal wall. The lower surface of the upper horizontal wall, an inner surface of the vertical wall, and an upper surface of the lower horizontal wall define a boundary of an outer plasma region, which surrounds the inner plasma region.

公开(公告)号：US10585347B2

公开(公告)日：2020-03-10

申请号：US16224651

申请日：2018-12-18

Applicant: Lam Research Corporation

Inventor： Saravanapriyan Sriraman ,  Richard Wise ,  Harmeet Singh ,  Alex Paterson ,  Andrew D. Bailey, III ,  Vahid Vahedi ,  Richard A. Gottscho

IPC: G03F1/36 ,  G06F17/50 ,  G03F1/80 ,  G03F1/70

Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

公开(公告)号：US20190393105A1

公开(公告)日：2019-12-26

申请号：US16015096

申请日：2018-06-21

Applicant: Lam Research Corporation

Inventor： Jea L. Cho ,  Daniel Anthony Simon ,  Andrew D. Bailey, III

IPC: H01L21/66 ,  H01L21/027 ,  H01L21/02 ,  G03F7/16 ,  C23C16/40 ,  C23C16/455

Abstract: Photoresist features can be characterized by electron microscopy-based metrology. A protective coating may be deposited on the photoresist with no change or minimal change to the dimensions of the underlying photoresist features, where the protective coating may be conformal and formed in a reactor operated under low temperature and low plasma conditions. In some implementations, the protective coating is formed by plasma-enhanced atomic layer deposition. Reliable and accurate profile information of photoresist features can be captured by metrology using the protective coating.

公开(公告)号：US20190311083A1

公开(公告)日：2019-10-10

申请号：US15946940

申请日：2018-04-06

Applicant: Lam Research Corporation

Inventor： Ye Feng ,  Marcus Musselman ,  Andrew D. Bailey, III ,  Mehmet Derya Tetiker ,  Saravanapriyan Sriraman ,  Yan Zhang ,  Julien Mailfert

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/80 ,  G03F1/86 ,  G03F1/78

Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

公开(公告)号：US10386821B2

公开(公告)日：2019-08-20

申请号：US14860009

申请日：2015-09-21

Applicant: Lam Research Corporation

Inventor： Marcus Musselman ,  Andrew D. Bailey, III

IPC: G05B19/418 ,  G01K3/06 ,  G01K15/00

Abstract: A system including a controller, an interface, and a calibration controller. The controller is configured to (i) select a set of fields, and (ii) based on the set of fields, supply control effort to first actuators in zones of a chamber. The interface is configured to receive feedback signals from sensors. The feedback signals are indicative of fields respectively of the zones. The controller is configured to adjust an amount of control effort supplied to the actuators based on the fields. The calibration controller is configured to, based on the fields, generate calibration values for each of the sensors. The calibration values for each of the sensors are indicative of field contributions corresponding respectively to the actuators.

公开(公告)号：US20190250501A1

公开(公告)日：2019-08-15

申请号：US16224651

申请日：2018-12-18

Applicant: Lam Research Corporation

Inventor： Saravanapriyan Sriraman ,  Richard Wise ,  Harmeet Singh ,  Alex Paterson ,  Andrew D. Bailey, III ,  Vahid Vahedi ,  Richard A. Gottscho

IPC: G03F1/36 ,  G03F1/80 ,  G03F1/70 ,  G06F17/50

Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

公开(公告)号：US10262910B2

公开(公告)日：2019-04-16

申请号：US15389451

申请日：2016-12-23

Applicant: Lam Research Corporation

Inventor： Ye Feng ,  Prashanth Kumar ,  Andrew D. Bailey, III

IPC: H01L21/66 ,  H01L21/67 ,  H01J37/32

Abstract: Methods and systems for using a time-series of spectra to identify endpoint of an etch process. One method includes accessing a virtual carpet that is formed from a time-series of spectra for the etch process collected during a training operation. And, running a fabrication etch process on a fabrication wafer, such that while the fabrication etch process is performed portions of a carpet defined from a time-series of spectral is generated for the fabrication etch process. Then, comparing the portions of the carpet of the fabrication etch process to the virtual carpet. End pointing is processed for the fabrication etch process when said comparing indicates that a desired metric has been reached for the fabrication wafer. In one example, said portions of the carpet include a current frame of captured spectra and at least one previous frame of captured spectra. The portions of the carpet of the fabrication etch process are fitted to the virtual carpet to identify a virtual frame number and associated floating parameters that are used in a correlation to predicted a value for the metric. Further, each of the carpets produced during the training operation and the virtual carpet are defined by a polynomial. The coefficients of the carpets produced during the training operation are a subset of the coefficients of the polynomial of the virtual carpet.

公开(公告)号：US10181412B2

公开(公告)日：2019-01-15

申请号：US14827052

申请日：2015-08-14

Applicant: Lam Research Corporation

Inventor： Alexei Marakhtanov ,  Mirzafer K. Abatchev ,  Rajinder Dhindsa ,  Eric Hudson ,  Andrew D. Bailey, III

IPC: C23C14/34 ,  C23C16/505 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/67 ,  H01L21/66 ,  H05H1/46

Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.

公开(公告)号：US09818633B2

公开(公告)日：2017-11-14

申请号：US14517623

申请日：2014-10-17

Applicant: Lam Research Corporation

Inventor： Thorsten Lill ,  Vahid Vahedi ,  Candi Kristoffersen ,  Andrew D. Bailey, III ,  Meihua Shen ,  Rangesh Raghavan ,  Gary Bultman

IPC: H01L21/677

CPC classification number: H01L21/67745 ,  H01L21/67766

Abstract: An EFEM useful for transferring wafers to and from wafer processing modules comprises an enclosure having a controlled environment therein bounded by a front wall, a back wall, first and second side walls, a top wall, and a bottom wall. The first side wall and the second side wall include two or more wafer load ports wherein each wafer load port is adapted to receive a FOUP. The front wall includes wafer ports configured to attach to respective load locks operable to allow a wafer to be transferred to a front wall cluster processing tool. The back wall includes a wafer port adapted to be in operational relationship with a back wall cluster processing tool. A robot in the EFEM enclosure is operable to transfer wafers through the wafer load ports, the first front wall wafer port, the second front wall wafer port, and the back wall wafer port.