公开(公告)号：US11209985B2

公开(公告)日：2021-12-28

申请号：US16391439

申请日：2019-04-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Sheng-Lun Wu ,  Chun-Lien Su ,  Zong-Qi Zhou

IPC: G06F3/06 ,  G06F9/30 ,  G06F1/3206

Abstract: An input/output delay optimization method, used in an electronic system comprising a host controller and a memory device. The method comprising: switching the memory device from a first mode to a second mode a high power consumption mode of the memory device; transmitting one or more first read commands to the memory device, wherein the one or more first read commands are transmitted according to different output delay values; determining an optimized output delay value according to the response status of memory device for the one or more first read commands; transmitting one or more second read commands to the memory device, wherein the one or more second read commands are transmitted according to the optimized output delay value; receiving a known data from the memory device according to different input delay values; and determining an optimized input delay value according to the correctness of the received known data.

公开(公告)号：US10217754B2

公开(公告)日：2019-02-26

申请号：US14278981

申请日：2014-05-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jung Tsai ,  Chun-Lien Su ,  Hsin-Fu Lin ,  Hung-Chi Chen

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L21/265 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78

Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.

公开(公告)号：US20150333077A1

公开(公告)日：2015-11-19

申请号：US14278981

申请日：2014-05-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jung Tsai ,  Chun-Lien Su ,  Hsin-Fu Lin ,  Hung-Chi Chen

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/265 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/42324 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881

Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.

Abstract translation: 提供了一种制造存储器件的方法，包括通过使用掩模层作为注入掩模来执行离子注入工艺，以便在衬底中形成第一嵌入掺杂区域和第二嵌入掺杂区域。 第一嵌入式掺杂区域沿着第一方向延伸，通过控制栅极，并且在控制栅极的两侧电连接到第一掺杂区域，第二掺杂区域和第三掺杂区域。 第二嵌入掺杂区域沿着第二方向延伸，位于第三掺杂区域下方的衬底中，并电连接到第三掺杂区域。 第一嵌入式掺杂区域电连接到第二嵌入掺杂区域。

公开(公告)号：US11487908B2

公开(公告)日：2022-11-01

申请号：US16542536

申请日：2019-08-16

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Lien Su

IPC: G06F21/00 ,  G06F21/83 ,  G06F3/06 ,  G06F11/10 ,  H04L9/32

Abstract: A memory controller, which manages a memory device, receives a memory command. The memory controller determines whether the memory command is encrypted. Upon determining that the memory command is encrypted, the memory controller performs a decryption function corresponding to the memory command. Conditioned on the performance of the decryption function resulting in a successful decryption of the memory command, the memory controller performs an operation on a memory location corresponding to a memory address included in the memory command.

公开(公告)号：US11455254B2

公开(公告)日：2022-09-27

申请号：US17118239

申请日：2020-12-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Chun-Lien Su ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC: G06F12/0882 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0862

Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

公开(公告)号：US20220180961A1

公开(公告)日：2022-06-09

申请号：US17115412

申请日：2020-12-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Chun-Lien Su

IPC: G11C29/52 ,  G11C29/42 ,  G11C29/44 ,  G11C29/46

Abstract: A memory device and a read method thereof are provided. The read method of the memory cell array includes: reading a memory cell array to obtain page data; dividing the page data into a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequence to respectively generate a plurality of first corrected chunk data; performing a second error correction operation on the page data to generate corrected page data; and outputting the corrected chunk data by referring to an indicating signal.

公开(公告)号：US11182302B2

公开(公告)日：2021-11-23

申请号：US16820795

申请日：2020-03-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Lien Su ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F12/08 ,  G06F12/0882 ,  G06F12/0862 ,  G11C7/22 ,  G06F9/30 ,  G06F12/0893

Abstract: A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.

公开(公告)号：US20210049309A1

公开(公告)日：2021-02-18

申请号：US16542536

申请日：2019-08-16

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Lien Su

IPC: G06F21/83 ,  G06F3/06 ,  G06F11/10 ,  H04L9/32

Abstract: A memory controller, which manages a memory device, receives a memory command. The memory controller determines whether the memory command is encrypted. Upon determining that the memory command is encrypted, the memory controller performs a decryption function corresponding to the memory command. Conditioned on the performance of the decryption function resulting in a successful decryption of the memory command, the memory controller performs an operation on a memory location corresponding to a memory address included in the memory command.

公开(公告)号：US20160307836A1

公开(公告)日：2016-10-20

申请号：US14687015

申请日：2015-04-15

Applicant: Macronix International Co., Ltd.

Inventor： Ya Jung TSai ,  Lan Ting Huang ,  Kuo NaiPing ,  Chun-Lien Su

IPC: H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L27/105

CPC classification number: H01L29/0847 ,  G11C7/18 ,  H01L27/0207

Abstract: A semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions, wherein each of the diffusion regions comprise source and drain regions of a bit line transistor pair comprising a first bit line transistor and a second bit line transistor and a plurality of bit line transistor gate pairs in contact with the respective diffusion region pairs, wherein the first bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of a first bit line transistor of the first diffusion region and the first bit lite transistor of the second diffusion region, wherein a second bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of the second bit line transistor of the first diffusion region and the second bit line transistor of the second diffusion layer.

Abstract translation: 提供一种半导体存储器件，其包括多个扩散区域对，其包括第一和第二扩散区域，其中每个扩散区域包括包含第一位线晶体管和第二位线晶体管的位线晶体管对的源区和漏区， 与相应的扩散区域对接触的多个位线晶体管栅极对，其中位线晶体管栅极对的第一位线晶体管栅极包括第一扩散区域的第一位线晶体管的栅极部分和第一位 位线晶体管栅极对的第二位线晶体管栅极包括第一扩散区域的第二位线晶体管的栅极部分和第二扩散层的第二位线晶体管。

公开(公告)号：US20140127894A1

公开(公告)日：2014-05-08

申请号：US14153897

申请日：2014-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Shaw-Hung Ku ,  Chi-Pei Lu ,  Chun-Lien Su

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract translation: 本发明提供了一种非易失性存储器的制造方法，包括在衬底上形成栅介质层; 在栅介质层上形成浮栅; 在浮栅上形成第一电荷阻挡层; 在所述第一电荷阻挡层上形成氮化物层; 在所述氮化物层上形成第二电荷阻挡层; 在所述第二电荷阻挡层上形成控制栅极; 并对氮化物层进行处理以获得更高的介电常数。