公开(公告)号：US20160204123A1

公开(公告)日：2016-07-14

申请号：US14596022

申请日：2015-01-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ta-Hone Yang ,  Shih-Ping Hong ,  Nan-Tsu Lian ,  Kuang-Chao Chen

IPC: H01L27/115 ,  H01L23/535 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L21/768 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/40117 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising providing a substrate and forming a plurality of layers over the substrate. The plurality of layers comprise alternating first composition material layers and second composition material layers. The method further comprises forming an elongated post. The post extends from at least the top surface of the substrate.

Abstract translation: 本示例实施例大体上涉及制造半导体器件的半导体器件和方法，包括提供衬底并在衬底上形成多个层。 多个层包括交替的第一组合物材料层和第二组合物材料层。 该方法还包括形成细长柱。 柱从至少衬底的顶表面延伸。

公开(公告)号：US20160172294A1

公开(公告)日：2016-06-16

申请号：US14571686

申请日：2014-12-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Sheng-Yuan Chang ,  An-Chyi Wei ,  Nan-Tsu Lian ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high aspect ratio structure is provided. The high aspect ratio structure includes a substrate, a plurality of stack structures, and a plurality of support structures. The stack structures are disposed on the substrate, and a trench is formed between adjacent two stack structures. Each of the stack structures includes a plurality of first material layers and a plurality of second material layers. The second material layers and the first material layers are disposed alternately. The support structures are respectively disposed between the substrate and the stack structures, wherein each of the support structures has a concave-convex surface.

Abstract translation: 提供了高纵横比结构。 高纵横比结构包括基板，多个堆叠结构和多个支撑结构。 堆叠结构设置在衬底上，并且在相邻的两个堆叠结构之间形成沟槽。 每个堆叠结构包括多个第一材料层和多个第二材料层。 第二材料层和第一材料层交替设置。 支撑结构分别设置在基板和堆叠结构之间，其中每个支撑结构具有凹凸表面。

公开(公告)号：US20150323583A1

公开(公告)日：2015-11-12

申请号：US14275437

申请日：2014-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsiang-Chou Liao ,  Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G01R31/04 ,  G01R31/305 ,  H01J37/28 ,  H01J37/22 ,  H01J37/244

CPC classification number: G01R31/04 ,  G01R31/305 ,  H01J37/222 ,  H01J37/244 ,  H01J37/28 ,  H01J2237/049 ,  H01J2237/063 ,  H01J2237/221 ,  H01J2237/24592 ,  H01J2237/2594 ,  H01J2237/28 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/14

Abstract: A method for detecting an electrical defect of contact/via plugs is provided. In the method, the contact/via plugs are monitored by an electron-beam (E-Beam) inspection tool to capture an image with a VC (voltage contrast) difference, and then an image extraction is performed on the image with the VC difference, wherein the image extraction is based on Target gray level/back ground gray level. The extracted image is contrasted with a layout design base to obtain a blind contact or Quasi-blind issue of contact/via plugs. A grayscale value of the VC difference having the blind contact or Quasi-blind issue is compared with a determined range of grayscale value to determine whether the VC difference is abnormal.

Abstract translation: 提供一种用于检测接触/通孔的电气缺陷的方法。 在该方法中，通过电子束（E-Beam）检查工具来监视接触/通孔塞以捕获具有VC（电压对比度）差异的图像，然后对具有VC差异的图像执行图像提取 ，其中所述图像提取基于目标灰度/背景灰度级。 提取的图像与布局设计基础形成对照，以获得接触/通孔插头的盲接或准盲问题。 将具有盲接或准盲问题的VC差的灰阶值与确定的灰度值范围进行比较，以确定VC差异是否异常。

公开(公告)号：US20150110384A1

公开(公告)日：2015-04-23

申请号：US14274177

申请日：2014-05-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiang-Chou Liao ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06T7/00

CPC classification number: G06T7/0006 ,  G06T2207/30148

Abstract: An image inspection method of die to database is provided, and the positions in the to-be-inspected chips within one wafer may be selected. In the method, a plurality of inspection areas in a plurality of positions in the to-be-inspected chips within a wafer are selected, a plurality of raw images of the inspection areas are obtained, and a plurality of locations of the raw images are then decoded. After that, an image extraction is performed on the raw images to obtain a plurality of image contours. Thereafter, the image contours are compared with a design database of the chip in order to obtain a result of a defect inspection, and execute the same thing in whole wafer.

Abstract translation: 提供了一种针对数据库的图像检查方法，并且可以选择在一个晶片内的待检查芯片中的位置。 在该方法中，选择在晶片内的待检查芯片的多个位置中的多个检查区域，获得检查区域的多个原始图像，原始图像的多个位置 然后解码。 之后，对原始图像执行图像提取以获得多个图像轮廓。 此后，将图像轮廓与芯片的设计数据库进行比较，以获得缺陷检查的结果，并在整个晶片中执行相同的事情。

公开(公告)号：US09466610B1

公开(公告)日：2016-10-11

申请号：US14666703

申请日：2015-03-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ta-Hone Yang

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/31 ,  H01L21/66 ,  H01L21/311 ,  H01L21/768 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/792 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/76802 ,  H01L21/76877 ,  H01L22/26 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure comprising providing a substrate; forming a plurality of layers having alternating first insulative material layers and second insulative material layers over the substrate; identifying bit line and word line locations for the formation of bit lines and word lines; removing at least a portion of the plurality of layers outside of the identified bit line and word line locations, each of the removed portions extending through the plurality of layers to at least a top surface of the substrate; forming a vertical first insulative material structure in the removed portions; performing an isotropic etching process to remove the second insulative material from the second insulative material layers; forming bit lines in the second insulative material layers within the identified bit line locations; and forming word lines in the identified word line locations.

Abstract translation: 现有示例实施例一般涉及制造三维门全（GAA）垂直栅（VG）半导体结构的方法，包括提供衬底; 在所述基板上形成具有交替的第一绝缘材料层和第二绝缘材料层的多个层; 识别用于形成位线和字线的位线和字线位置; 去除所识别的位线和字线位置之外的多个层中的至少一部分，每个去除的部分延伸穿过多个层到至少衬底的顶表面; 在去除部分中形成垂直的第一绝缘材料结构; 执行各向同性蚀刻工艺以从所述第二绝缘材料层去除所述第二绝缘材料; 在所识别的位线位置内的第二绝缘材料层中形成位线; 并在所识别的字线位置中形成字线。

公开(公告)号：US20160284725A1

公开(公告)日：2016-09-29

申请号：US14666703

申请日：2015-03-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ta-Hone Yang

IPC: H01L27/115 ,  H01L21/31 ,  H01L21/66 ,  H01L21/311 ,  H01L23/528 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/76802 ,  H01L21/76877 ,  H01L22/26 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure comprising providing a substrate; forming a plurality of layers having alternating first insulative material layers and second insulative material layers over the substrate; identifying bit line and word line locations for the formation of bit lines and word lines; removing at least a portion of the plurality of layers outside of the identified bit line and word line locations, each of the removed portions extending through the plurality of layers to at least a top surface of the substrate; forming a vertical first insulative material structure in the removed portions; performing an isotropic etching process to remove the second insulative material from the second insulative material layers; forming bit lines in the second insulative material layers within the identified bit line locations; and forming word lines in the identified word line locations.

Abstract translation: 现有示例实施例一般涉及制造三维门全（GAA）垂直栅（VG）半导体结构的方法，包括提供衬底; 在所述基板上形成具有交替的第一绝缘材料层和第二绝缘材料层的多个层; 识别用于形成位线和字线的位线和字线位置; 去除所识别的位线和字线位置之外的多个层中的至少一部分，每个去除的部分延伸穿过多个层到至少衬底的顶表面; 在去除部分中形成垂直的第一绝缘材料结构; 执行各向同性蚀刻工艺以从所述第二绝缘材料层去除所述第二绝缘材料; 在所识别的位线位置内的第二绝缘材料层中形成位线; 并在所识别的字线位置中形成字线。

公开(公告)号：US20150357203A1

公开(公告)日：2015-12-10

申请号：US14296862

申请日：2014-06-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Ta-Hone Yang

IPC: H01L21/32 ,  H01L27/115 ,  H01L21/266 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3065 ,  H01J37/32899

Abstract: A patterning method is described. A patterned mask layer is formed on a material layer, having therein a first opening exposing a portion of the material layer. A pre-treatment process is performed to modify the material layer exposed in the first opening and form a modified region therein. An etching process is performed to remove the material layer in the modified region at least and form a second opening in the material layer.

Abstract translation: 描述图案化方法。 图案化的掩模层形成在材料层上，其中具有暴露材料层的一部分的第一开口。 执行预处理工艺以改变在第一开口中暴露的材料层，并在其中形成改性区域。 进行蚀刻处理，以至少在材料层中除去改性区域中的材料层并形成第二开口。

公开(公告)号：US09116108B1

公开(公告)日：2015-08-25

申请号：US14178293

申请日：2014-02-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G01N23/225

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: An electron beam (E beam) inspection optimization is provided, in which a plurality of initial inspection regions in a chip are obtained, wherein a center of each of the initial inspection regions is a defect point. Thereafter, reset inspection regions are regenerated without overlap, wherein each of the reset inspection regions is within a scope covered by a field of view (FOV) and the scope contains at least one of the defect points. Afterwards, a center of the reset inspection region is transferred into an inspection center, and then an E beam inspection is performed on the inspection center.

Abstract translation: 提供了一种电子束（E光束）检查优化，其中获得了芯片中的多个初始检查区域，其中每个初始检查区域的中心是缺陷点。 此后，复位检查区域不重叠地再生，其中每个复位检查区域在由视场（FOV）覆盖的范围内，并且范围包含至少一个缺陷点。 然后，将复位检查区域的中心转移到检查中心，然后在检查中心进行E光束检查。

公开(公告)号：US20150226687A1

公开(公告)日：2015-08-13

申请号：US14178293

申请日：2014-02-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G01N23/225

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: An electron beam (E beam) inspection optimization is provided, in which a plurality of initial inspection regions in a chip are obtained, wherein a center of each of the initial inspection regions is a defect point. Thereafter, reset inspection regions are regenerated without overlap, wherein each of the reset inspection regions is within a scope covered by a field of view (FOV) and the scope contains at least one of the defect points. Afterwards, a center of the reset inspection region is transferred into an inspection center, and then an E beam inspection is performed on the inspection center.

Abstract translation: 提供了一种电子束（E光束）检查优化，其中获得芯片中的多个初始检查区域，其中每个初始检查区域的中心是缺陷点。 此后，复位检查区域不重叠地再生，其中每个复位检查区域在由视场（FOV）覆盖的范围内，并且范围包含至少一个缺陷点。 然后，将复位检查区域的中心转移到检查中心，然后在检查中心进行E光束检查。

公开(公告)号：US20150213172A1

公开(公告)日：2015-07-30

申请号：US14165043

申请日：2014-01-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiang-Chou Liao ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/50 ,  G01Q30/02

CPC classification number: G06F17/5045 ,  G02B21/002 ,  H01J37/28 ,  H01J2237/221 ,  H01J2237/2817

Abstract: A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Abstract translation: 提供了一种用于测量芯片或晶片的表面结构的方法，其包括获得芯片的表面结构的图像，然后对图像执行图像提取以将提取的图像转换为第一电路设计文件。 选择标准图像以转换为第二电路设计文件，然后比较图像中的标准图像和至少一个目标，以获得它们之间的差异。 根据差异，可以进行表面结构的至少一个数据，其中数据从线边缘粗糙度（LER），线宽粗糙度（LWR），接触边缘粗糙度（CER），临界尺寸（CD） ），偏置，3西格玛，最大值，最小值等，并重复缺陷。