公开(公告)号：US20150023098A1

公开(公告)日：2015-01-22

申请号：US13943691

申请日：2013-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0475 ,  G11C16/3422

Abstract: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.

Abstract translation: 提供了多级存储器的操作方法。 将低于标准读取电压的第一读取电压施加到存储器的控制栅极的一侧的衬底中的掺杂区域，以便确定第一存储位置和第二存储位置是否都处于最低级 。

公开(公告)号：US09625520B2

公开(公告)日：2017-04-18

申请号：US14792148

申请日：2015-07-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: G01R31/00 ,  G01R31/28 ,  G01R1/04

CPC classification number: G01R31/2853 ,  G01R1/0491 ,  G01R31/3004

Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.

公开(公告)号：US09460928B2

公开(公告)日：2016-10-04

申请号：US14612359

申请日：2015-02-03

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Han Chou ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L21/70 ,  H01L21/265 ,  H01L21/66 ,  H01L29/167 ,  H01L27/115 ,  H01L21/8232

CPC classification number: H01L21/26586 ,  H01L21/8232 ,  H01L22/12 ,  H01L22/20 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833

Abstract: A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.

Abstract translation: 半导体器件制造方法包括制备具有形成在基板上的突起的晶片。 所述突出部从所述基板的表面向上突出，并且具有从所述基板的表面测量的高度。 该方法还包括确定表示相邻投影之间的间隔的分布的间隔分布，并基于高度和间隔分布计算植入角度。 注入角度是基板的法线方向与注入方向之间的角度。 该方法还包括以所计算的植入角度注入离子。

公开(公告)号：US20150194808A1

公开(公告)日：2015-07-09

申请号：US14272115

申请日：2014-05-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Yu Wang ,  Tao-Cheng Lu ,  Yao-Wen Chang

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0259

Abstract: An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased.

Abstract translation: 提供一种包括PNP晶体管，保护电路和调整电路的静电放电保护装置。 PNP晶体管的发射极电连接到焊盘，并且PNP晶体管的集电极电连接到地。 保护电路电连接在PNP晶体管的基极与地之间，并提供放电路径。 当在焊盘上发生静电信号时，静电信号通过放电路径和PNP晶体管传导到地面。 调节电路电连接在PNP晶体管的发射极和基极之间。 当向焊盘提供电源电压时，调节电路根据电源电压向PNP晶体管的基极提供控制电压，以防止PNP晶体管的发射极和基极正向偏置。

公开(公告)号：US08937347B2

公开(公告)日：2015-01-20

申请号：US14266079

申请日：2014-04-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L21/4763 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.

Abstract translation: 提供非易失性存储器。 非易失性存储器包括氧化物和多晶硅堆叠结构和电荷存储层。 氧化物和多晶硅堆叠结构设置在基板上。 在氧化物和多晶硅堆叠结构两侧的衬底中有凹槽。 氧化物和多晶硅堆叠结构包括氧化物层和多晶硅层。 氧化物层设置在衬底上，其中在氧化物层和衬底之间存在界面。 多晶硅层设置在氧化物层上。 电荷存储层设置在凹槽中并延伸到氧化物和多晶硅堆叠结构的侧壁，并且每个电荷存储层的顶表面高于界面。

公开(公告)号：US20140231900A1

公开(公告)日：2014-08-21

申请号：US14266079

申请日：2014-04-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.

Abstract translation: 提供非易失性存储器。 非易失性存储器包括氧化物和多晶硅堆叠结构和电荷存储层。 氧化物和多晶硅堆叠结构设置在基板上。 在氧化物和多晶硅堆叠结构两侧的衬底中有凹槽。 氧化物和多晶硅堆叠结构包括氧化物层和多晶硅层。 氧化物层设置在衬底上，其中在氧化物层和衬底之间存在界面。 多晶硅层设置在氧化物层上。 电荷存储层设置在凹槽中并延伸到氧化物和多晶硅堆叠结构的侧壁，并且每个电荷存储层的顶表面高于界面。

公开(公告)号：US09443955B2

公开(公告)日：2016-09-13

申请号：US14539768

申请日：2014-11-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.

Abstract translation: 提供一种半导体器件。 两个堆叠层设置在第一导电类型的衬底上。 每个堆叠层包括电介质层和导电层。 电介质层设置在基板上。 导电层设置在电介质层上。 第二导电类型的第一掺杂区具有第一掺杂剂并且被布置在堆叠层之间的衬底中。 在第一掺杂区域中设置预非晶化注入（PAI）区域。 第二导电类型的第二掺杂区域具有第二掺杂剂并且被布置在PAI区域中。 第一导电类型与第二导电类型不同。 第二掺杂剂的扩散速度比第一掺杂剂的扩散速度快，并且第二掺杂剂的热激活高于第一掺杂剂的扩散速率。

公开(公告)号：US09324789B1

公开(公告)日：2016-04-26

申请号：US14723094

申请日：2015-05-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: H01L29/788 ,  H01L29/06 ,  H01L27/115 ,  H01L21/764 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The memory device is provided to include a substrate, a plurality of stack structures, conductive pillars, charge storage layers, and third conductive layers. The stack structures are arranged along a first direction and extend along a second direction, wherein each stack structure includes a plurality of first conductive layers and a plurality of dielectric layers that are alternately stacked along a third direction. Each conductive pillar is located on the substrate between two adjacent stack structures. Each charge storage layer is disposed between the stack structures and the conductive pillars. Each third conductive layer extending along the first direction overlaps the stack structures in a plurality of overlapped regions and covers a portion of top parts of the stack structures and the conductive pillars. An air gap is formed along the third direction in each overlapped region where the stacked structures and the third conductive layers overlap.

Abstract translation: 存储器件被设置为包括衬底，多个堆叠结构，导电柱，电荷存储层和第三导电层。 堆叠结构沿着第一方向布置并且沿着第二方向延伸，其中每个堆叠结构包括多个第一导电层和沿着第三方向交替堆叠的多个电介质层。 每个导电柱位于两个相邻堆叠结构之间的衬底上。 每个电荷存储层设置在堆叠结构和导电柱之间。 沿着第一方向延伸的每个第三导电层在多个重叠区域中重叠堆叠结构并覆盖堆叠结构的顶部部分和导电柱。 在堆叠结构和第三导电层重叠的重叠区域中沿着第三方向形成气隙。

公开(公告)号：US20150194420A1

公开(公告)日：2015-07-09

申请号：US14150638

申请日：2014-01-08

Applicant: Macronix International Co., Ltd.

Inventor： Shih Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L27/02 ,  H01L29/08

CPC classification number: H01L27/0262 ,  H01L27/0266 ,  H01L29/74 ,  H01L29/861

Abstract: A semiconductor device includes a substrate, and first and second wells formed in the substrate. The first well has a first conductivity type. The second well has a second conductivity type different than the first conductivity type. The device includes a first heavily-doped region having the first conductivity type and a second heavily-doped region having the first conductivity type. A portion of the first heavily-doped region is formed in the first well. The second heavily-doped region is formed in the second well. The device also includes an insulating layer formed over a channel region of the substrate between the first and second heavily-doped regions, and a gate electrode formed over the insulating layer. The device further includes a terminal for coupling to a circuit being protected, and a switching circuit coupled between the terminal and the first heavily-doped region, and between the terminal and the gate electrode.

Abstract translation: 半导体器件包括衬底以及形成在衬底中的第一阱和第二阱。 第一阱具有第一导电类型。 第二阱具有与第一导电类型不同的第二导电类型。 该器件包括具有第一导电类型的第一重掺杂区和具有第一导电类型的第二重掺杂区。 在第一阱中形成第一重掺杂区的一部分。 在第二阱中形成第二重掺杂区域。 该器件还包括在第一和第二重掺杂区域之间的衬底的沟道区域上形成的绝缘层，以及形成在绝缘层上的栅电极。 该器件还包括用于耦合到被保护的电路的端子，以及耦合在端子和第一重掺杂区域之间以及端子和栅电极之间的开关电路。

公开(公告)号：US20140159134A1

公开(公告)日：2014-06-12

申请号：US13707426

申请日：2012-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.

Abstract translation: 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括设置在衬底上的栅极结构，掺杂区域，电荷存储层和第一介电层。 栅极结构两侧的基板上有凹槽。 栅极结构包括设置在衬底上的栅极电介质层和设置在栅极介电层上的栅极。 在栅介电层和衬底之间存在界面。 掺杂区域围绕凹部设置在基板中。 电荷存储层设置在凹部中，并且每个电荷存储层的顶表面高于界面。 第一介电层设置在电荷存储层与基板之间，电荷存储层与栅极结构之间。