公开(公告)号：US20160365407A1

公开(公告)日：2016-12-15

申请号：US14739717

申请日：2015-06-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Teng-Hao YEH

IPC: H01L49/02 ,  H01L27/06 ,  H01L27/115

CPC classification number: H01L28/90 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/60

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

Abstract translation: 集成电路包括具有导电条的堆叠的3D NAND存储器阵列和具有堆叠的电容器端子条的电容器。 导电带堆叠中的多个导电条和电容器端子条的堆叠的多个电容器端子条相对于基板共享相同的多个平面位置。 在相同多个平面位置中的不同平面位置表示电容器端子条的堆叠中的不同的电容器端子条和导电条的堆叠中的不同的导电条，以及表征导电条的堆叠中的导电条的同一平面位置 电容器端子排堆叠中的电容器端子条表示导电条和电容器端子条相对于彼此具有相同的垂直位置。

公开(公告)号：US20150179575A1

公开(公告)日：2015-06-25

申请号：US14617420

申请日：2015-02-09

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei HU ,  Teng-Hao YEH

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L23/535 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/41766 ,  H01L29/788 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Abstract translation: 一种器件包括具有凹陷的基底，具有底部和侧面，从基底的上表面延伸到基底中。 侧面包括横向彼此定向的第一和第二侧面。 交替的有源绝缘层和绝缘层的堆叠覆盖在衬底的表面和凹部上。 活性层中的至少一些具有分别在上表面和下平面上方并且大体上平行于上表面和底部延伸的上部和下部。 有源层具有沿着第一和第二侧定位的第一和第二向上延伸，以从它们各自的有源层的下部延伸。 导电带邻接所述有源层的第二向上延伸。 导电条可以包括在第二向上延伸部分的侧面上的侧壁间隔物，导电条通过层间导体连接到覆盖的导体。

公开(公告)号：US20230009065A1

公开(公告)日：2023-01-12

申请号：US17368700

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4096 ,  G11C5/06

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20220246195A1

公开(公告)日：2022-08-04

申请号：US17321664

申请日：2021-05-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Kai HSU ,  Teng-Hao YEH ,  Hang-Ting LUE

IPC: G11C11/408 ,  G11C11/4074 ,  G11C15/04 ,  G11C5/06 ,  H03K19/017

Abstract: A three-dimension (3D) memory device and an operation method thereof are provided. The 3D memory device includes: a memory array including a plurality of memory cells; a controller coupled to the memory array; and a match circuit coupled to memory array, wherein in data search and match, the controller selects from the memory cells a plurality of target memory cells sharing a same target global signal line, and the controller selects a plurality of target word lines sharing the target global signal line as a plurality of target search lines, wherein a search data sends to the target memory cells via the target search lines for data matching; the target global signal line is precharged; and outputting a match address based on whether a voltage on the target global signal line is pulled down or not.

公开(公告)号：US20220020761A1

公开(公告)日：2022-01-20

申请号：US16931598

申请日：2020-07-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.

公开(公告)号：US20210241081A1

公开(公告)日：2021-08-05

申请号：US16872404

申请日：2020-05-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Lin SUNG ,  Teng-Hao YEH

IPC: G06N3/063 ,  G11C11/54 ,  G11C16/24 ,  G11C16/26 ,  G06N3/04

Abstract: A spiking neural networks circuit and an operation method thereof are provided. The spiking neural networks circuit includes a bit-line input synapse array and a neuron circuit. The bit-line input synapse array includes a plurality of page buffers, a plurality of bit line transistors, a plurality of bit lines, a plurality of memory cells, one word line, a plurality of source lines and a plurality of source line transistors. The page buffers provides a plurality of data signals. Each of the bit line transistors is electrically connected to one of the page buffers. Each of the bit lines receives one of the data signals. The source line transistors are connected together. The neuron circuit is for outputting a feedback pulse.

公开(公告)号：US20210159243A1

公开(公告)日：2021-05-27

申请号：US16693507

申请日：2019-11-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.

公开(公告)号：US20200243555A1

公开(公告)日：2020-07-30

申请号：US16257165

申请日：2019-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28

Abstract: A memory device and a manufacturing method for the same are provided. The memory device comprises a stack structure and a channel structure. The stack structure is on a substrate and comprises gate electrodes and insulating films stacked alternately. The channel structure is electrically coupled to the gate electrodes, and is on sidewall surfaces of the gate electrodes. The channel structure comprises a first channel structure and a second channel structure. The second channel structure is on an upper surface of the first channel structure. The first channel structure and/or the second channel structure has a ring shape.

公开(公告)号：US20250107110A1

公开(公告)日：2025-03-27

申请号：US18471292

申请日：2023-09-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU ,  Cheng-Yu LEE

IPC: H10B99/00

Abstract: Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

公开(公告)号：US20220375523A1

公开(公告)日：2022-11-24

申请号：US17325243

申请日：2021-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng LIN ,  Su-Chueh LO ,  Teng-Hao YEH ,  Hang-Ting LUE

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.