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    Patterned Remote Direct Memory Access (RDMA)
    14.
    发明公开
    Patterned Remote Direct Memory Access (RDMA) 审中-公开

    公开(公告)号：US20240015217A1

    公开(公告)日：2024-01-11

    申请号：US17858097

    申请日：2022-07-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

    IPC: H04L67/1097

    CPC classification number: H04L67/1097

    Abstract: A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

    INTERRUPT EMULATION ON NETWORK DEVICES
    15.
    发明公开
    INTERRUPT EMULATION ON NETWORK DEVICES 审中-公开

    公开(公告)号：US20230315659A1

    公开(公告)日：2023-10-05

    申请号：US17707555

    申请日：2022-03-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Liran Liss ,  Rabia Loulou ,  Aviad Yehezkel

    IPC: G06F13/24 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173

    CPC classification number: G06F13/24 ,  G06F13/4221 ,  G06F15/17331 ,  G06F13/4022 ,  G06F13/4072

    Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

    Out-of-order packet processing
    18.
    发明申请
    Out-of-order packet processing 有权

    公开(公告)号：US20230074989A1

    公开(公告)日：2023-03-09

    申请号：US17987911

    申请日：2022-11-16

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Yamin Friedman ,  Daniel Marcovitch ,  Gil Levy

    IPC: H04L47/34 ,  H04L1/18

    Abstract: In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the tinier is activated responsively to a quantity of the multiple missing data packets.

    Out-of-order packet processing
    19.
    发明授权
    Out-of-order packet processing 有权

    公开(公告)号：US12218852B2

    公开(公告)日：2025-02-04

    申请号：US18524010

    申请日：2023-11-30

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Yamin Friedman ,  Daniel Marcovitch ,  Gil Levy

    IPC: H04L47/34 ,  H04L1/18

    Abstract: In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the timer is activated responsively to a quantity of the multiple missing data packets.

    Network Adapter Providing Address Translation as a Service
    20.
    发明申请
    Network Adapter Providing Address Translation as a Service 有权

    公开(公告)号：US20250028648A1

    公开(公告)日：2025-01-23

    申请号：US18353123

    申请日：2023-07-17

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Eliav Bar-Ilan ,  Liran Liss

    IPC: G06F12/1072 ,  H04L67/1097

    Abstract: A network adapter including a host interface, a network interface, packet processing circuitry, and Translation-as-a-Service (TaaS) circuitry. The host interface is to communicate with a host over a peripheral bus. The network interface is to send and receive packets to and from a network for the host. The packet processing circuitry is to process the packets. The TaaS circuitry is integrated in the network adapter and is to (i) receive from a requesting device a request to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.

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