公开(公告)号：US12068272B2

公开(公告)日：2024-08-20

申请号：US18059165

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kunal R. Parekh ,  Aaron S. Yip

IPC: H01L25/18 ,  H01L23/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L24/20 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11574685B2

公开(公告)日：2023-02-07

申请号：US17443841

申请日：2021-07-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

Abstract: Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.

公开(公告)号：US20210288071A1

公开(公告)日：2021-09-16

申请号：US17208868

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/08 ,  G11C11/56 ,  H01L21/768 ,  H01L21/3213 ,  G11C16/24

Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

公开(公告)号：US20210272633A1

公开(公告)日：2021-09-02

申请号：US17321604

申请日：2021-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/10 ,  G11C16/26 ,  G11C11/56

Abstract: Methods of operating a memory, and memories configured to perform such methods, might include applying a programming pulse having a plurality of different voltage levels to a selected access line during a programming operation, and for each group of memory cells of a plurality of groups of memory cells of a plurality of memory cells selected for programming, enabling that group of memory cells for programming during a respective portion of the duration of the programming pulse of a corresponding voltage level of the plurality of different voltage levels, wherein memory cells of the plurality of memory cells selected for programming and having a particular intended data state are members of more than one of the groups of memory cells, and at least one of the groups of memory cells comprises a memory cell having the particular intended data state and a memory cell having a different intended data state

公开(公告)号：US20200327922A1

公开(公告)日：2020-10-15

申请号：US16913115

申请日：2020-06-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C11/408 ,  G11C7/10 ,  G11C16/08 ,  G11C7/12 ,  G11C8/08

Abstract: Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, with each driver circuitry connected to a respective block of memory cells.

公开(公告)号：US20200051612A1

公开(公告)日：2020-02-13

申请号：US16101600

申请日：2018-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C11/408 ,  G11C7/10 ,  G11C16/08 ,  G11C8/08 ,  G11C7/12

Abstract: Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, each driver circuitry connected to a respective block of memory cells, as well as methods of operating such memories.

公开(公告)号：US20190213073A1

公开(公告)日：2019-07-11

申请号：US16352530

申请日：2019-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Mark A. Helm ,  Aaron S. Yip

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F3/06 ,  H03M13/00 ,  H03M13/37 ,  G11C16/26 ,  G11C16/08

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/08 ,  G11C7/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/5641 ,  H03M13/1111 ,  H03M13/1177 ,  H03M13/2909 ,  H03M13/3723 ,  H03M13/612

Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.

公开(公告)号：US10289484B2

公开(公告)日：2019-05-14

申请号：US15267844

申请日：2016-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Mark A. Helm ,  Aaron S. Yip

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/52 ,  H03M13/11 ,  H03M13/37 ,  H03M13/00 ,  G11C29/04 ,  H03M13/29

Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.

公开(公告)号：US10037806B2

公开(公告)日：2018-07-31

申请号：US15665474

申请日：2017-08-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/26

Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to selected memory cells of a programming operation, assigning the selected memory cells to respective groups of memory cells each having a different range of threshold voltages, determining a respective value of VgVt for each group of memory cells, applying a subsequent programming pulse to the selected access line and having a particular voltage level determined in response to the value of VgVt for a particular group of memory cells, enabling the selected memory cells of the particular group of memory cells for programming while the subsequent programming pulse has the particular voltage level, and repeating for a next group of memory cells.

公开(公告)号：US10014061B1

公开(公告)日：2018-07-03

申请号：US15484369

申请日：2017-04-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip ,  Mark A. Helm

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each of the strings of series-connected memory cells is selectively connected to the same data line through a respective plurality of select gates connected in series between that string and the data line. One select gate of each of the pluralities of select gates has a threshold voltage within a first range of threshold voltages, and each remaining select gate of each of the pluralities of select gates has a threshold voltage within a second range of threshold voltages mutually exclusive from the first range of threshold voltages. Each of the select gates having a threshold voltage within the first range of threshold voltages has its control gate isolated from any of the other select gates having a threshold voltage within the first range of threshold voltages.