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    SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED METHODS
    11.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED METHODS 有权
    包括平台步骤结构的半导体器件及相关方法

    公开(公告)号：US20150001613A1

    公开(公告)日：2015-01-01

    申请号：US13932551

    申请日：2013-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip ,  Qiang Tang ,  Chang Wan Ha

    IPC: H01L23/50 ,  H01L27/115

    CPC classification number: H01L27/11556 ,  G11C16/06 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.

    Abstract translation: 诸如三维存储器件的半导体器件包括包括导电层堆叠和阶梯结构的存储器阵列。 阶梯结构位于存储器阵列的第一和第二部分之间，并且包括用于导电层叠层的相应导电层的接触区域。 存储器阵列的第一部分包括在堆叠上沿特定方向延伸的第一多个选择栅极。 存储器阵列的第二部分包括第二多个选择栅极，其也沿着导电层叠层的特定方向延伸。 还公开了形成方法和操作这种半导体器件的方法，包括垂直存储器件。

    SELECT GATE PROGRAMMING IN A MEMORY DEVICE
    12.
    发明申请
    SELECT GATE PROGRAMMING IN A MEMORY DEVICE 有权
    在存储器中选择编程

    公开(公告)号：US20140003151A1

    公开(公告)日：2014-01-02

    申请号：US14018926

    申请日：2013-09-05

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada ,  Aaron Yip

    IPC: G11C16/10

    CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

    Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.

    Abstract translation: 公开了用于编程选择门，存储器件和存储器系统的方法。 在一种用于编程的方法中，程序禁止电压从源传输到未选位线。 在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。 在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。

    Reducing programming disturbance in memory devices
    13.
    发明授权
    Reducing programming disturbance in memory devices 有权

    公开(公告)号：US12080360B2

    公开(公告)日：2024-09-03

    申请号：US18195181

    申请日：2023-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24

    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
    14.
    发明申请
    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES 有权

    公开(公告)号：US20210287754A1

    公开(公告)日：2021-09-16

    申请号：US17157443

    申请日：2021-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/10

    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

    Reducing programming disturbance in memory devices
    15.
    发明授权
    Reducing programming disturbance in memory devices 有权

    公开(公告)号：US10902927B2

    公开(公告)日：2021-01-26

    申请号：US16784899

    申请日：2020-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/24

    Abstract: Apparatus and methods are provided, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are provided.

    MEMORY DEVICES INCLUDING STAIR STEP OR TIERED STRUCTURES AND RELATED METHODS
    16.
    发明申请
    MEMORY DEVICES INCLUDING STAIR STEP OR TIERED STRUCTURES AND RELATED METHODS 审中-公开

    公开(公告)号：US20190259703A1

    公开(公告)日：2019-08-22

    申请号：US16405184

    申请日：2019-05-07

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

    IPC: H01L23/528 ,  H01L27/11575 ,  H01L21/768 ,  H01L23/522

    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

    Memories having select devices between access lines and in memory cells
    17.
    发明授权
    Memories having select devices between access lines and in memory cells 有权

    公开(公告)号：US10249345B2

    公开(公告)日：2019-04-02

    申请号：US16039559

    申请日：2018-07-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron Yip

    IPC: G11C5/06 ,  G11C13/00 ,  G11C7/18

    Abstract: Memories may include a first bi-directional select device connected between a first access line and a second access line, and a plurality of memory cells, each memory cell of the plurality of memory cells connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells comprises a respective second bi-directional select device, of a plurality of second bi-directional select devices, and a respective programmable element, of a plurality of programmable elements, connected in series.

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