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公开(公告)号：US20240036743A1
公开(公告)日：2024-02-01
申请号：US18379343
申请日：2023-10-12
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Carly M. Wantulok , Sumana Adusumilli , Chiara Cerafogli
CPC classification number: G06F3/0619 , G06F3/0623 , G06N20/00 , G06F3/0659 , G06F3/067 , G06F3/0656
Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with data transmission are described. Data transmission management can include receiving, from an edge device via a radio at a first device, instructions associated with data transmission between a second device in communication with the first device and a cloud service in communication with the first device. Data transmission management can also include managing, at the first device and based on the instructions from the edge device, data received from a memory resource of the second device for transmission to the cloud service and data received from the cloud service for transmission to the memory resource of the second device. Data transmission management can further include enabling transmission of some, none, or all of the data between the cloud service and the memory resource of the second device and vice versa based on the management of the data.
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公开(公告)号：US11823743B2
公开(公告)日：2023-11-21
申请号：US17747516
申请日：2022-05-18
Applicant: Micron Technology, Inc.
Inventor： Shannon Marissa Hansen , Fulvio Rori , Andrea D'Alessandro , Jason Lee Nevill , Chiara Cerafogli
CPC classification number: G11C16/20 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/24 , G11C16/26 , H10B41/27 , H10B43/27
Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.
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公开(公告)号：US20230367495A1
公开(公告)日：2023-11-16
申请号：US17663137
申请日：2022-05-12
Applicant: Micron Technology, Inc.
Inventor： Lalla Fatima Drissi , Anna Scalesse , Iolanda Del Villano , Maddalena Calzolari , Chiara Cerafogli , Carla L. Christensen
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0659 , G06F3/0616 , G06F3/0619 , G06F3/0679
Abstract: Methods, systems, and devices for host-enabled block swap techniques are described. In some examples, a host system may receive an indication of a health metric associated with a first physical block and a second physical block of a memory system, where a first logical block of the memory system is associated with a first type of data and is mapped to the first physical block, and where a second logical block of the memory system is associated with a second type of data. The host system may then determine that the health metric associated with the first physical block satisfies a threshold and may update a mapping associated with the first virtual block, the second virtual block, the first physical block, and the second physical block.
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公开(公告)号：US20220342561A1
公开(公告)日：2022-10-27
申请号：US17236183
申请日：2021-04-21
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Carly M. Wantulok , Sumana Adusumilli , Chiara Cerafogli
Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with data transmission are described. Data transmission management can include receiving, from an edge device via a radio at a first device, instructions associated with data transmission between a second device in communication with the first device and a cloud service in communication with the first device. Data transmission management can also include managing, at the first device and based on the instructions from the edge device, data received from a memory resource of the second device for transmission to the cloud service and data received from the cloud service for transmission to the memory resource of the second device. Data transmission management can further include enabling transmission of some, none, or all of the data between the cloud service and the memory resource of the second device and vice versa based on the management of the data.
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公开(公告)号：US11189536B2
公开(公告)日：2021-11-30
申请号：US16294469
申请日：2019-03-06
Applicant: Micron Technology, Inc.
Inventor： Kenneth William Marr , Chiara Cerafogli , Michele Piccardi , Marco-Domenico Tiburzi , Eric Higgins Freeman , Joshua Daniel Tomayer
Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.
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Patent Agency Ranking
公开(公告)号：US11170860B2
公开(公告)日：2021-11-09
申请号：US16787199
申请日：2020-02-11
Applicant: Micron Technology, Inc.
Inventor： Fulvio Rori , Chiara Cerafogli
Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.
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公开(公告)号：US20210043525A1
公开(公告)日：2021-02-11
申请号：US16535882
申请日：2019-08-08
Applicant: Micron Technology, Inc.
Inventor： Chiara Cerafogli , Kenneth William Marr , Brian J. Soderling , Michael P. Violette , Joshua Daniel Tomayer , James E. Davis
IPC: H01L21/66 , H01L27/11556 , H01L23/00 , H01L23/528 , H01L27/11526 , H01L27/11573 , H03K3/03 , H01L27/11582 , G11C16/26 , G11C16/08 , G11C16/04 , G11C29/14
Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.
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18.发明授权公开(公告)号：US10580506B2
公开(公告)日：2020-03-03
申请号：US15835129
申请日：2017-12-07
Applicant: Micron Technology, Inc.
Inventor： Fulvio Rori , Chiara Cerafogli
Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.
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公开(公告)号：US20200004458A1
公开(公告)日：2020-01-02
申请号：US16023130
申请日：2018-06-29
Applicant: Micron Technology, Inc.
Inventor： Chiara Cerafogli , Fulvio Rori , Jonathan W. Oh , Giuseppe Cariello
Abstract: Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.
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公开(公告)号：US20240354027A1
公开(公告)日：2024-10-24
申请号：US18638476
申请日：2024-04-17
Applicant: Micron Technology, Inc.
Inventor： Chiara Cerafogli , Carla L. Christensen , Iolanda Del Villano , Lalla Fatima Drissi , Anna Scalesse , Maddalena Calzolari
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/064 , G06F3/0679
Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.
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