公开(公告)号：US20240185926A1

公开(公告)日：2024-06-06

申请号：US18517903

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Kishore Kumar Mucherla ,  William Charles Filipiak ,  Eric N. Lee ,  Andrew Bicksler ,  Ugo Russo ,  Niccolo' Righetti ,  Christian Caillat ,  Akira Goda ,  Ting Luo ,  Antonino Pollio

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/16 ,  G11C16/3404

Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.

公开(公告)号：US09633719B2

公开(公告)日：2017-04-25

申请号：US14724945

申请日：2015-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: Embodiments of methods and memory devices for performing the methods are disclosed. In an embodiment, one such method includes programming all memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level and respectively programming all the memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.

公开(公告)号：US09093311B2

公开(公告)日：2015-07-28

申请号：US14299577

申请日：2014-06-09

Applicant: Micron Technology, Inc.

Inventor： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I. Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/1095 ,  H01L21/76264 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891 ,  H01L29/7841

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Abstract translation: 公开了一种用于提供半导体存储器件的技术。 在一个实施例中，可以将技术实现为包括以行和列的阵列布置的多个存储单元的半导体存储器件。 每个存储器单元可以包括连接到以第一取向延伸的源极线的第一区域，连接到延伸第二取向的位线的第二区域以及与字线间隔开并且电容耦合到字线的主体区域，其中所述主体 区域是电浮动的并且设置在第一区域和第二区域之间。 半导体器件还可以包括沿阵列的第一取向延伸的第一阻挡壁和在阵列的第二取向延伸并且与第一阻挡壁相交的第二阻挡壁，以形成沟槽区域，该沟槽区域被配置为容纳多个 的记忆细胞。

公开(公告)号：US11778806B2

公开(公告)日：2023-10-03

申请号：US17388678

申请日：2021-07-29

Applicant: Micron Technology, Inc.

Inventor： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC: G11C11/34 ,  H10B12/00 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4094 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B12/20 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  H01L29/24 ,  H10B12/50 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US20190088343A1

公开(公告)日：2019-03-21

申请号：US16186739

申请日：2018-11-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: Apparatus including an array of memory cells and a controller configured to program all memory cells of a grouping of memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level, and to respectively program all the memory cells of the grouping of memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.

公开(公告)号：US20180211714A1

公开(公告)日：2018-07-26

申请号：US15933498

申请日：2018-03-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.

公开(公告)号：US09779829B2

公开(公告)日：2017-10-03

申请号：US14943541

申请日：2015-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian Caillat ,  Akira Goda

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16

Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.

公开(公告)号：US20170178737A1

公开(公告)日：2017-06-22

申请号：US15437584

申请日：2017-02-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.

公开(公告)号：US20160351253A1

公开(公告)日：2016-12-01

申请号：US14724945

申请日：2015-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: Embodiments of methods and memory devices for performing the methods are disclosed. In an embodiment, one such method includes programming all memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level and respectively programming all the memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.

Abstract translation: 公开了用于执行方法的方法和存储装置的实施例。 在一个实施例中，一种这样的方法包括将所有存储器单元编程为分别被编程到除了最低数据状态的最低级别之外的不同级别，从最低级别编程到中间级别，并分别编程所有存储器单元 分别被编程到不同于最低级别的不同级别，而不是从中间级别的最低级别以外的不同级别。