公开(公告)号：US10163655B2

公开(公告)日：2018-12-25

申请号：US14948074

申请日：2015-11-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jin Lu ,  Rita J. Klein ,  Diem Thy N. Tran ,  Irina V. Vasilyeva ,  Zhiqiang Xie

IPC: H01L29/40 ,  H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/48

Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.

公开(公告)号：US20180301454A1

公开(公告)日：2018-10-18

申请号：US16006301

申请日：2018-06-12

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum SImsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/405 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US10079235B2

公开(公告)日：2018-09-18

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20180061836A1

公开(公告)日：2018-03-01

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20200243536A1

公开(公告)日：2020-07-30

申请号：US16258933

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Diem Thy N. Tran ,  Sanjeev Sapra

IPC: H01L27/108 ,  H01L27/105

Abstract: Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.

公开(公告)号：US20190267379A1

公开(公告)日：2019-08-29

申请号：US16412750

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L29/10 ,  H01L29/78

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US10242726B1

公开(公告)日：2019-03-26

申请号：US16180542

申请日：2018-11-05

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/24 ,  G11C11/402 ,  H01L27/108 ,  G11C5/06

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US10153027B1

公开(公告)日：2018-12-11

申请号：US16106617

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: H01L27/118 ,  G11C11/402 ,  G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US10083734B1

公开(公告)日：2018-09-25

申请号：US15804981

申请日：2017-11-06

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/24 ,  G11C11/402 ,  H01L27/108 ,  G11C5/06

CPC classification number: G11C11/4023 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/4097 ,  G11C2207/105 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10855 ,  H01L27/10885

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US10056386B2

公开(公告)日：2018-08-21

申请号：US15664217

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L29/10 ,  H01L49/02 ,  H01L27/02 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L27/108 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/10864 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/945

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.