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    Sensing techniques for a memory cell
    12.
    发明授权
    Sensing techniques for a memory cell 有权

    公开(公告)号：US11289147B2

    公开(公告)日：2022-03-29

    申请号：US17165529

    申请日：2021-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

    IPC: G11C7/00 ,  G11C11/22

    Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

    Single plate configuration and memory array operation
    18.
    发明授权
    Single plate configuration and memory array operation 有权

    公开(公告)号：US11626151B2

    公开(公告)日：2023-04-11

    申请号：US16983469

    申请日：2020-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina

    IPC: G11C11/22 ,  G06F13/16

    Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

    Memory device with single transistor drivers and methods to operate the memory device
    19.
    发明授权
    Memory device with single transistor drivers and methods to operate the memory device 有权

    公开(公告)号：US11545219B2

    公开(公告)日：2023-01-03

    申请号：US16975619

    申请日：2020-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

    IPC: G11C7/00 ,  G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

    Abstract: A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.

    PARALLEL ACCESS FOR MEMORY SUBARRAYS
    20.
    发明申请
    PARALLEL ACCESS FOR MEMORY SUBARRAYS 有权

    公开(公告)号：US20220013157A1

    公开(公告)日：2022-01-13

    申请号：US17381976

    申请日：2021-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Efrem Bolandrina

    IPC: G11C8/08 ,  G06F3/06 ,  G11C11/22 ,  G11C11/408 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096

    Abstract: Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

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