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    Memory Arrays And Methods Used In Forming A Memory Array
    15.
    发明申请
    Memory Arrays And Methods Used In Forming A Memory Array 审中-公开

    公开(公告)号：US20200168622A1

    公开(公告)日：2020-05-28

    申请号：US16200158

    申请日：2018-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Yoshiaki Fukuzumi ,  M. Jared Barclay ,  Emilio Camerlenghi ,  Paolo Tessariol

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28

    Abstract: A method used in forming a memory array comprises forming a tier comprising conductor material above a substrate. Sacrificial islands comprising etch-stop material are formed directly above the conductor material of the tier comprising the conductor material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the sacrificial islands and the tier comprising the conductor material. Etching is conducted through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material. The sacrificial islands are removed through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material. Channel material is formed in the extended-channel openings to the tier comprising the conductor material. The channel material is electrically coupled with the conductor material of the tier comprising the conductor material. Structure independent of method is disclosed.

    Methods of forming memory arrays
    16.
    发明授权
    Methods of forming memory arrays 有权
    形成记忆阵列的方法

    公开(公告)号：US09214389B2

    公开(公告)日：2015-12-15

    申请号：US14265168

    申请日：2014-04-29

    Applicant: Micron Technology, Inc.

    Inventor： Niccolo′ Righetti ,  Sara Vigano ,  Emilio Camerlenghi

    IPC: H01L21/76 ,  H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

    Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

    Abstract translation: 一些实施例包括形成存储器阵列的方法。 形成了在较低水平上具有较高水平的组件。 下层包括电路。 上层包括存储器阵列区域内的半导体材料，并且在存储器阵列区域周围的区域中包括绝缘材料。 第一和第二沟槽形成为延伸到半导体材料中。 第一和第二沟槽将半导体材料图案化成多个基座。 第二沟槽延伸到周边区域。 在周边区域内形成接触开口以从第二沟槽延伸到电路的第一级。 导电材料形成在第二沟槽内部和接触开口内。 导电材料在第二沟槽内形成感测/接入线，并在接触开口内形成电接触，以将感测/接入线电耦合到较低级别的电路。

    Methods of Forming Memory Arrays
    17.
    发明申请
    Methods of Forming Memory Arrays 有权
    形成记忆阵列的方法

    公开(公告)号：US20150311115A1

    公开(公告)日：2015-10-29

    申请号：US14265168

    申请日：2014-04-29

    Applicant: Micron Technology, Inc.

    Inventor： Niccolo' Righetti ,  Sara Vigano ,  Emilio Camerlenghi

    IPC: H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

    Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

    Abstract translation: 一些实施例包括形成存储器阵列的方法。 形成了在较低水平上具有较高水平的组件。 下层包括电路。 上层包括存储器阵列区域内的半导体材料，并且在存储器阵列区域周围的区域中包括绝缘材料。 第一和第二沟槽形成为延伸到半导体材料中。 第一和第二沟槽将半导体材料图案化成多个基座。 第二沟槽延伸到周边区域。 在周边区域内形成接触开口以从第二沟槽延伸到电路的第一级。 导电材料形成在第二沟槽内部和接触开口内。 导电材料在第二沟槽内形成感测/接入线，并在接触开口内形成电接触，以将感测/接入线电耦合到较低级别的电路。

    Erasing memory
    18.
    发明授权
    Erasing memory 有权

    公开(公告)号：US12190961B2

    公开(公告)日：2025-01-07

    申请号：US17988090

    申请日：2022-11-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

    Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.

    ERASING MEMORY
    19.
    发明申请
    ERASING MEMORY 有权

    公开(公告)号：US20230078036A1

    公开(公告)日：2023-03-16

    申请号：US17988090

    申请日：2022-11-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

    Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.

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