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公开(公告)号：US09202586B2
公开(公告)日：2015-12-01
申请号：US14554794
申请日：2014-11-26
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Giovanni Santin , Michele Incarnati
CPC classification number: G11C16/34 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459
Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.
Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括将信号施加到与存储器单元相关联的线，该信号是基于数字信息生成的。 该方法还可以包括当信号被施加到线路时，当数字信息具有第一值时，确定存储器单元的状态是否接近目标状态，并且确定存储器单元的状态是否已经达到目标 当数字信息具有第二值时状态。 描述包括附加存储器件和方法的其它实施例。
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公开(公告)号：US09042184B2
公开(公告)日：2015-05-26
申请号：US13925192
申请日：2013-06-24
Applicant: Micron Technology, Inc.
Inventor： Paul D. Ruby , Violante Moschiano , Giovanni Santin
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3459
Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.
Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法包括在编程操作期间将电压施加到与不同组的存储器单元相关联的数据线。 这种方法将电压施加到与已编程其它存储器单元组之后，以与存储器单元的其他组相同的方式编程的最后一组存储器单元相关联的数据线。 描述包括附加存储器件和方法的其它实施例。
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13.发明申请LINE VOLTAGE BOOST SYSTEM AND METHOD FOR NON-VOLATILE MEMORY DEVICES AND MEMORY DEVICES AND PROCESSOR-BASED SYSTEM USING SAME 有权用于非易失性存储器件和存储器件的线路电压升压系统和方法以及使用其的基于处理器的系统公开(公告)号：US20140204674A1
公开(公告)日：2014-07-24
申请号：US14223734
申请日：2014-03-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Giovanni Santin , Ercole Di Iorio
IPC: G11C16/12
Abstract: The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.
Abstract translation: 所选择的字线的电压通过从相邻字线电容耦合到所选字线的电压而增加到相应的串驱动晶体管能够驱动字线的电压。 在将编程电压施加到所选字线的串驱动晶体管之后，并且在将串驱动器电压施加到所有字的栅极之后，通过增加相邻字线的电压来将电压电容耦合到所选择的字线 的阵列驱动晶体管。
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公开(公告)号：US20140133224A1
公开(公告)日：2014-05-15
申请号：US14162278
申请日：2014-01-23
Applicant: Micron Technology, Inc.
Inventor： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC: G11C16/34
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
Abstract translation: 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：US08705277B2
公开(公告)日：2014-04-22
申请号：US13834412
申请日：2013-03-15
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Giovanni Santin
IPC: G11C16/00
CPC classification number: G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459
Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described.
Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法包括基于处于擦除状态的存储器单元的阈值电压将不同的电压施加到与不同存储器单元相关联的数据线。 描述包括附加存储器件和方法的其它实施例。
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Patent Agency Ranking
公开(公告)号：US20140043912A1
公开(公告)日：2014-02-13
申请号：US14045492
申请日：2013-10-03
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
Abstract translation: 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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公开(公告)号：US10446258B2
公开(公告)日：2019-10-15
申请号：US15721994
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Giovanni Santin , Maria-Luisa Gallese , Luigi Pilolli
Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.
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公开(公告)号：US20180047460A1
公开(公告)日：2018-02-15
申请号：US15721994
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Giovanni Santin , Maria-Luisa Gallese , Luigi Pilolli
CPC classification number: G11C29/846 , G11C16/0483 , G11C29/76 , G11C29/82 , G11C2229/723
Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.
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公开(公告)号：US09558831B2
公开(公告)日：2017-01-31
申请号：US14715169
申请日：2015-05-18
Applicant: Micron Technology, Inc.
Inventor： Paul D. Ruby , Violante Moschiano , Giovanni Santin
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3459
Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.
Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法包括在编程操作期间将电压施加到与不同组的存储器单元相关联的数据线。 这种方法将电压施加到与已编程其它存储器单元组之后，以与存储器单元的其他组相同的方式编程的最后一组存储器单元相关联的数据线。 描述包括附加存储器件和方法的其它实施例。
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20.发明授权公开(公告)号：US09305660B2
公开(公告)日：2016-04-05
申请号：US14012602
申请日：2013-08-28
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Giovanni Santin
CPC classification number: G11C16/3436 , G11C11/56 , G11C11/5628 , G11C16/00 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C16/3481 , G11C2029/0409
Abstract: Apparatus and methods for determining pass/fail condition of memories facilitate array efficiencies. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.
Abstract translation: 用于确定存储器的通过/失败状态的装置和方法有助于阵列效率。 在至少一个实施例中，对于与页面相对应的每个页面缓冲器等级的一组公共线路确定所有连接的存储器单元的通过/失败状态，并且可以将每行的通过/失败状态结果组合 确定内存页面的通过/失败。
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