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    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    14.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11925016B2

    公开(公告)日：2024-03-05

    申请号：US17400598

    申请日：2021-08-12

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: G11C5/06 ,  G11C5/02 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76838 ,  H10B43/27

    Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Conducting material of a lowest of the conductive tiers is directly against the conductor material of the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The conducting material in the lowest conductive tier is directly against the channel material of individual of the channel-material strings. Conductive material is of different composition from that of the conducting material above and directly against the conducting material. Other embodiments, including method, are disclosed.

    Memory Circuitry And Method Used In Forming Memory Circuitry
    15.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240074183A1

    公开(公告)日：2024-02-29

    申请号：US17897516

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. Multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The multiple different-depth treads in the individual stairs comprise a first flight of the treads and a second flight of the treads. A landing is between and lower in the stack than each of the first and second flights of treads. The first and second flights of treads in the second direction face toward one another. Methods are disclosed.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    19.
    发明公开
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20230397420A1

    公开(公告)日：2023-12-07

    申请号：US17830108

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Nancy M. Lomeli ,  Jordan D. Greenlee

    IPC: H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tier. Conducting material is formed in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The forming of the conducting material comprises forming conductive material in the lower first tier against the channel material of the individual channel-material strings. The conductive material comprises an upper portion and a lower portion having a void-space vertically there-between. The void-space comprises an exposed silicon-containing surface. Silicon is selectively deposited into the void-space onto and from the exposed silicon-containing surface. Other embodiments, including structure independent of method, are disclosed.

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