公开(公告)号：US11565371B2

公开(公告)日：2023-01-31

申请号：US16237051

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: B24B53/04 ,  B24B53/065 ,  B24B3/36 ,  B24B3/46 ,  B24B53/07 ,  B24D15/06 ,  B24B53/017 ,  B24B37/02 ,  B24B53/12

Abstract: A dressing board for sharpening and/or shaping blades for manufacture of semiconductor devices can include a working surface configured to sharpen and/or shape a cutting surface of a dicing or edging blade for manufacture of a semiconductor device. The working surface can be configured to contact the cutting surface of the blade when sharpening or shaping the cutting surface. The dressing board can include a support substrate configured to support the working surface with respect to a floor of an enclosure in which the dressing board is positioned. In some embodiments, the working surface includes a first portion that is not parallel to the floor.

公开(公告)号：US11527505B2

公开(公告)日：2022-12-13

申请号：US17102253

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  G06F30/394

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

公开(公告)号：US20200373252A1

公开(公告)日：2020-11-26

申请号：US16993860

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

公开(公告)号：US20190311918A1

公开(公告)日：2019-10-10

申请号：US16436461

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US10262961B2

公开(公告)日：2019-04-16

申请号：US15982129

申请日：2018-05-17

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US20160358898A1

公开(公告)日：2016-12-08

申请号：US14730681

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

Abstract translation: 制造半导体器件封装的方法可以包括将第一半导体管芯附接到载体晶片，第一半导体管芯的面向载体晶片的非活性表面。 一个或多个附加的半导体管芯可以在第一半导体管芯上与第一半导体管芯的与载体晶片相对的一侧堆叠以形成半导体管芯堆叠。 保护材料可以位于半导体管芯的堆叠之上，保护材料的一部分沿着第一半导体管芯的侧表面延伸到接近第一半导体管芯的非活性表面的位置。 载体晶片可以与第一半导体管芯分离。

公开(公告)号：US20240222145A1

公开(公告)日：2024-07-04

申请号：US18602553

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3157 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/91 ,  H01L24/83 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/26145 ,  H01L2224/29023 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/18161

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US20210041495A1

公开(公告)日：2021-02-11

申请号：US17083193

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Tony M. Lindenberg ,  Kurt J. Bossart ,  Jonathan S. Hacker ,  Chandra S. Tiwari

IPC: G01R31/28 ,  H01L21/67 ,  G01R1/073 ,  H01L21/68

Abstract: A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3D interconnect (3DI) structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

公开(公告)号：US20200206869A1

公开(公告)日：2020-07-02

申请号：US16237051

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Hacker

IPC: B24B53/017 ,  B24B53/07 ,  B24B53/12 ,  B24B37/02

Abstract: A dressing board for sharpening and/or shaping blades for manufacture of semiconductor devices can include a working surface configured to sharpen and/or shape a cutting surface of a dicing or edging blade for manufacture of a semiconductor device. The working surface can be configured to contact the cutting surface of the blade when sharpening or shaping the cutting surface. The dressing board can include a support substrate configured to support the working surface with respect to a floor of an enclosure in which the dressing board is positioned. In some embodiments, the working surface includes a first portion that is not parallel to the floor.

公开(公告)号：US20200083178A1

公开(公告)日：2020-03-12

申请号：US16127769

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.