公开(公告)号：US20250054898A1

公开(公告)日：2025-02-13

申请号：US18789266

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor device, including a lower semiconductor die, one or more upper semiconductor dies disposed over the lower semiconductor die, a non-conductive fillet material disposed between adjacent semiconductor dies of the lower semiconductor die and the one or more upper semiconductor dies, the non-conductive fillet material having edge regions that squeeze out from space between adjacent semiconductor dies, a dielectric layer disposed on a backside of the lower semiconductor die and under the one or more upper semiconductor dies, a buffer layer disposed above the dielectric layer and in contact to at least one edge region of the non-conductive fillet material, and an encapsulant material disposed on sidewalls and top surface of the semiconductor device, the encapsulant material encapsulating the lower semiconductor die and the one or more upper semiconductor dies.

公开(公告)号：US20250008750A1

公开(公告)日：2025-01-02

申请号：US18736187

申请日：2024-06-06

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kunal R. Parekh

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device with a through via between redistribution layers is disclosed. The semiconductor device includes a stack of semiconductor dies coupled with first contact pads on a first redistribution layer. The first redistribution layer further includes a second contact pad located outside the footprint of the die stack and circuitry coupling the second contact pad to the first contact pads. A gap fill is disposed around the stack of semiconductor dies. A second redistribution layer is disposed at the stack of semiconductor dies and the gap fill. The second redistribution layer includes third contact pads coupled with the stack of semiconductor dies, a fourth contact pad disposed beyond the footprint of the stack of semiconductor dies, fifth contact pads opposite the third and fourth contact pads, and circuitry coupling the contact pads. A through via is disposed through the gap fill coupling the second and fourth contact pads.

公开(公告)号：US20250006704A1

公开(公告)日：2025-01-02

申请号：US18736318

申请日：2024-06-06

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor device with a spaced supply voltage and ground reference is disclosed. A stack of semiconductor dies includes a first semiconductor die, one or more second semiconductor dies, and first and second contacts. A gap fill is disposed over a distal end of the one or more second semiconductor dies opposite the first semiconductor die. A first rail (e.g., supply voltage) is disposed at a distal end of the gap fill opposite the first semiconductor die, and a first via extends from the first rail to the first contact. A layer of dielectric material is disposed at least partially over the first rail. A second rail (e.g., ground reference) is disposed at the layer of dielectric material, and a second via extends from the second rail to the second contact. Third and fourth exposed contacts are coupled to the first and second rails, respectively.

公开(公告)号：US20240413021A1

公开(公告)日：2024-12-12

申请号：US18668106

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kunal R. Parekh

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/78 ,  H01L25/18

Abstract: Methods, apparatuses, and systems related to a semiconductor apparatus having one or more dielectric structures used to detect bonding voids during manufacturing. In some embodiments, a semiconductor wafer includes the dielectric structures. After the wafer is bonded to another structure, capacitances may be measured across the dielectric structures and the other wafer. The measured capacitance can be used to detect or characterize any bonding voids that may have been introduced during the wafer bonding process.

公开(公告)号：US20240412980A1

公开(公告)日：2024-12-12

申请号：US18667983

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L21/3205 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die has a first layer of dielectric material and a first conductive pad disposed in a first opening of the first layer of dielectric material. The second semiconductor die has a second layer of dielectric material facing the first layer of dielectric material and a second conductive pad disposed in a second opening of the second layer of dielectric material and corresponding to the first conductive pad. A spacer extends between the first layer of dielectric material and the second layer of dielectric material. A conductive material is disposed between the first conductive pad and the second conductive pad (e.g., through atomic layer deposition (ALD)) to implement an interconnect electrically coupling the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240379503A1

公开(公告)日：2024-11-14

申请号：US18780303

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US12080678B2

公开(公告)日：2024-09-03

申请号：US17881572

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/75 ,  H01L23/481 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/75317 ,  H01L2224/81203 ,  H01L2224/95091

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

公开(公告)号：US20240071968A1

公开(公告)日：2024-02-29

申请号：US18199741

申请日：2023-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Terrence B. McDaniel ,  Wei Zhou

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/80365 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0554 ,  H01L2924/059

Abstract: This document discloses techniques, apparatuses, and systems for semiconductor device interconnects formed through volumetric expansion. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die and the second semiconductor die are bonded at a dielectric layer of the first semiconductor die and a dielectric layer of the second semiconductor die to create one or more interconnect openings. The first semiconductor die includes a reservoir of conductive material located adjacent to the one or more interconnect openings and having a width greater than a width of the one or more interconnect openings. The reservoir of conductive material is heated to volumetrically expand the reservoir of conductive material through the one or more interconnect openings to form one or more interconnects electrically coupling the first semiconductor die and the second semiconductor die. In this way, a connected semiconductor device may be assembled.

公开(公告)号：US20240047424A1

公开(公告)日：2024-02-08

申请号：US17883486

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05609 ,  H01L2224/05639 ,  H01L2224/0579 ,  H01L2224/05799 ,  H01L2224/80379

Abstract: Semiconductor dies and devices, such as memory dies and devices, and associated systems and methods, are disclosed herein. A representative semiconductor die comprises a substrate including a first surface, a second surface opposite the first surface, a perimeter, and a recess formed into the first surface adjacent to the perimeter. The recess has a depth in a direction extending between the first surface and the second surface. The semiconductor die further comprises a first bonding structure on the first surface and a second bonding structure on the second surface. The first bonding structure has a thickness, and the depth is at least ten times greater than the thickness. The recess can facilitate mechanical debonding of the semiconductor die during a manufacturing process that includes stacking the semiconductor die within a semiconductor device package.

公开(公告)号：US20230343673A1

公开(公告)日：2023-10-26

申请号：US17728625

申请日：2022-04-25

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Amy R. Griffin

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3737 ,  H01L23/3735 ,  H01L23/3675 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L24/96 ,  H01L24/97 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2924/1436 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2224/08221 ,  H01L2224/80896

Abstract: A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.