公开(公告)号：US20230395430A1

公开(公告)日：2023-12-07

申请号：US18140523

申请日：2023-04-27

Applicant: Micron Technology, Inc.

Inventor： Marc Anthony Romana de Guzman ,  Aibin Yu ,  Bee Sei Soh

IPC: H01L21/78 ,  H01L29/06

CPC classification number: H01L21/78 ,  H01L29/0657

Abstract: A semiconductor device can include a semiconductor substrate singulated from a device wafer having had multiple semiconductor devices formed thereon. The semiconductor substrate can include a first corner, a first sidewall extends in a first direction from the first corner, and a second sidewall extending in a second direction from the first corner. The first sidewall can include a first laser modification extending along the first direction and the second sidewall can include a second laser modification extending along the second direction. A portion of the second sidewall between the first corner and the second laser modification can (i) exclude laser modification, or (ii) the second laser modification can be offset from the first corner along the second direction.

公开(公告)号：US20210175194A1

公开(公告)日：2021-06-10

申请号：US17174827

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

公开(公告)号：US10734370B2

公开(公告)日：2020-08-04

申请号：US16396235

申请日：2019-04-26

Applicant: Micron Technology, Inc.

Inventor： Zhaohui Ma ,  Wei Zhou ,  Chee Chung So ,  Soo Loo Ang ,  Aibin Yu

IPC: H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L21/683 ,  H01L21/78

Abstract: Methods of making semiconductor device packages may involve cutting kerfs in streets between regions of a semiconductor wafer and positioning stacks of semiconductor dice on portions of surfaces of at least some adjacent regions. A protective material may be dispensed only between the stacks of the semiconductor dice, over the exposed remainders of the regions, and in the kerfs. A back side of the semiconductor wafer may be ground to a final thickness, revealing the protective material in the kerfs at a side of the semiconductor wafer opposite the stacks of the semiconductor dice. The protective material between the stacks of the semiconductor dice and within the kerfs may be cut through, leaving the protective material on sides of the semiconductor dice of the stacks and on side surfaces of the regions within the kerfs.

公开(公告)号：US20190252362A1

公开(公告)日：2019-08-15

申请号：US16396235

申请日：2019-04-26

Applicant: Micron Technology, Inc.

Inventor： Zhaohui Ma ,  Wei Zhou ,  Chee Chung So ,  Soo Loo Ang ,  Aibin Yu

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/544 ,  H01L21/683

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of making semiconductor device packages may involve cutting kerfs in streets between regions of a semiconductor wafer and positioning stacks of semiconductor dice on portions of surfaces of at least some adjacent regions. A protective material may be dispensed only between the stacks of the semiconductor dice, over the exposed remainders of the regions, and in the kerfs. A back side of the semiconductor wafer may be ground to a final thickness, revealing the protective material in the kerfs at a side of the semiconductor wafer opposite the stacks of the semiconductor dice. The protective material between the stacks of the semiconductor dice and within the kerfs may be cut through, leaving the protective material on sides of the semiconductor dice of the stacks and on side surfaces of the regions within the kerfs.

公开(公告)号：US10103134B2

公开(公告)日：2018-10-16

申请号：US15728123

申请日：2017-10-09

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L29/40 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

公开(公告)号：US12255128B2

公开(公告)日：2025-03-18

申请号：US17676037

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Yee Chon Chin

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a package substrate and a silicon spacer disposed on an upper surface of the substrate, the silicon spacer having a plurality of trenches extending into the silicon spacer from a top surface thereof. The semiconductor device assembly further includes one or more semiconductor devices disposed over the silicon spacer. Moreover, the semiconductor device assembly includes an encapsulant material at least partially encapsulating the one or more semiconductor devices and the package substrate, the encapsulant material at least partially filling the plurality of trenches of the silicon spacer.

公开(公告)号：US20240429190A1

公开(公告)日：2024-12-26

申请号：US18827181

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

公开(公告)号：US20190109019A1

公开(公告)日：2019-04-11

申请号：US16203538

申请日：2018-11-28

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Zhaohui Ma ,  Aibin Yu

IPC: H01L21/48 ,  H01L25/00 ,  H01L23/373 ,  H01L25/065 ,  H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L23/367 ,  H01L23/31 ,  H01L21/78

Abstract: Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.

公开(公告)号：US20160358898A1

公开(公告)日：2016-12-08

申请号：US14730681

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

Abstract translation: 制造半导体器件封装的方法可以包括将第一半导体管芯附接到载体晶片，第一半导体管芯的面向载体晶片的非活性表面。 一个或多个附加的半导体管芯可以在第一半导体管芯上与第一半导体管芯的与载体晶片相对的一侧堆叠以形成半导体管芯堆叠。 保护材料可以位于半导体管芯的堆叠之上，保护材料的一部分沿着第一半导体管芯的侧表面延伸到接近第一半导体管芯的非活性表面的位置。 载体晶片可以与第一半导体管芯分离。

公开(公告)号：US20160233110A1

公开(公告)日：2016-08-11

申请号：US15134788

申请日：2016-04-21

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Zhaohui Ma ,  Aibin Yu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/4882 ,  H01L21/4878 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/4334 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/29191 ,  H01L2224/293 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15787

Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.