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    DETERMINING DATA STATES OF MEMORY CELLS
    11.
    发明申请
    DETERMINING DATA STATES OF MEMORY CELLS 审中-公开

    公开(公告)号：US20190267102A1

    公开(公告)日：2019-08-29

    申请号：US16410406

    申请日：2019-05-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

    IPC: G11C16/26 ,  G06F11/07 ,  G11C11/56 ,  G11C29/02

    Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

    Configurable operating mode memory device and methods of operation
    12.
    发明授权
    Configurable operating mode memory device and methods of operation 有权

    公开(公告)号：US10261713B2

    公开(公告)日：2019-04-16

    申请号：US15945316

    申请日：2018-04-04

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge

    IPC: G06F3/06 ,  G11C11/00 ,  G11C15/04 ,  G06F11/22 ,  G06F11/10 ,  G11C16/04

    Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

    Methods of operating memory
    13.
    发明授权
    Methods of operating memory 有权

    公开(公告)号：US10068653B2

    公开(公告)日：2018-09-04

    申请号：US15241496

    申请日：2016-08-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

    IPC: G11C16/10 ,  G11C16/26 ,  G06N3/04 ,  G06N3/063 ,  G11C16/04 ,  G11C7/10 ,  G11C16/08

    Abstract: Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.

    MEMORY AS A PROGRAMMABLE LOGIC DEVICE
    19.
    发明申请
    MEMORY AS A PROGRAMMABLE LOGIC DEVICE 有权
    作为可编程逻辑器件的存储器

    公开(公告)号：US20160232978A1

    公开(公告)日：2016-08-11

    申请号：US15132455

    申请日：2016-04-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

    IPC: G11C16/10 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

    Abstract: Methods for operating memory cells include applying a respective minterm, comprising a plurality of variables, to control gates of series strings of memory cells, each series string programmed as a plurality of pairs of complementary memory cells such that certain ones of the plurality of variables are enabled, and logically combining each of the minterms into a logic function output. Memories include a plurality of memory cells configured in series strings of memory cells, wherein each series string of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell.

    Abstract translation: 用于操作存储器单元的方法包括应用包括多个变量的相应最小值来控制存储器单元的串联串的栅极，每个串行串被编程为多对互补存储器单元，使得多个变量中的某些变量是 启用并逻辑地将每个minterms组合成逻辑功能输出。 存储器包括配置成串联的存储器单元串的多个存储器单元，其中存储器单元的每个串联串被配置为提供包括多个变量的最小值，每个变量响应于相关联的相应存储单元的状态而启用。

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