公开(公告)号：US20180315457A1

公开(公告)日：2018-11-01

申请号：US16029046

申请日：2018-07-06

Applicant: Micron Technology, Inc.

Inventor： Mamoru Nishizaki

IPC: G11C5/02 ,  H01L27/108 ,  G11C29/00 ,  G11C11/4097 ,  G11C8/10 ,  G11C7/18 ,  G11C5/06 ,  G11C11/408

CPC classification number: G11C5/025 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C11/4087 ,  G11C11/4097 ,  G11C29/00 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/1204 ,  H01L27/108

Abstract: Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.

公开(公告)号：US12094522B2

公开(公告)日：2024-09-17

申请号：US17936785

申请日：2022-09-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akeno Ito ,  Mamoru Nishizaki

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4096

Abstract: An apparatus that includes: a plurality of first data amplifiers arranged in line in a first direction; a plurality of first read data buses each coupled to a corresponding one of the plurality of first data amplifiers, the plurality of first read data buses having different lengths one another; and a plurality of first write data buses each coupled to the corresponding one of the plurality of first data amplifiers, the plurality of first write data buses having different lengths one another. The plurality of first read data buses and the plurality of first write data buses are alternately arranged in parallel in a second direction vertical to the first direction. The plurality of first read data buses are arranged in longest order and the plurality of first write data buses are arranged in shortest order.

公开(公告)号：US11715522B2

公开(公告)日：2023-08-01

申请号：US17359268

申请日：2021-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akeno Ito ,  Takayori Hamada ,  Mamoru Nishizaki

IPC: G11C16/08 ,  G11C16/30 ,  H10B12/00

CPC classification number: G11C16/08 ,  G11C16/30 ,  H10B12/50

Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.

公开(公告)号：US20220415397A1

公开(公告)日：2022-12-29

申请号：US17359268

申请日：2021-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akeno Ito ,  Takayori Hamada ,  Mamoru Nishizaki

IPC: G11C16/08 ,  G11C16/30 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.

公开(公告)号：US10020038B1

公开(公告)日：2018-07-10

申请号：US15488328

申请日：2017-04-14

Applicant: Micron Technology, Inc.

Inventor： Mamoru Nishizaki

IPC: G11C5/06 ,  G11C8/12 ,  G11C7/10 ,  G11C5/02

CPC classification number: G11C5/025 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C11/4087 ,  G11C11/4097 ,  G11C29/00 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/1204 ,  H01L27/108

Abstract: Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.

公开(公告)号：US20150035054A1

公开(公告)日：2015-02-05

申请号：US14447976

申请日：2014-07-31

Applicant: Micron Technology, Inc.

Inventor： Mamoru Nishizaki

IPC: H01L29/423 ,  H01L27/02 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/42376 ,  G06F1/3287 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/7817 ,  Y02D10/171

Abstract: A device includes a first transistor including a first gate electrode including first and second parallel electrode portions each extending in a first direction, and a first connecting electrode portion extending in a second direction approximately orthogonal to the first direction and connecting one ends of the first and second parallel electrode portions to each other, and first and second diffusion layers separated from each other by a channel region under the first gate electrode, a first output line connected to the first diffusion layer of the first transistor, and a second transistor comprising a second gate electrode extending in the second direction, and the second transistor being configured to use the second diffusion layer of the first transistor as one of two diffusion layers that are separated from each other by a channel region under the second gate electrode.

Abstract translation: 一种器件包括：第一晶体管，包括第一栅电极，第一栅电极包括分别沿第一方向延伸的第一和第二平行电极部分;以及第一连接电极部分，其沿大致正交于第一方向的第二方向延伸，并且连接第一和 第二平行电极部分彼此分开，并且第一和第二扩散层通过第一栅电极下方的沟道区彼此分离，第一输出线连接到第一晶体管的第一扩散层，第二晶体管包括第二 栅电极沿第二方向延伸，第二晶体管被配置为将第一晶体管的第二扩散层用作通过第二栅电极下方的沟道区彼此分离的两个扩散层之一。

公开(公告)号：US20250069647A1

公开(公告)日：2025-02-27

申请号：US18749464

申请日：2024-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hirokazu Ato ,  Mamoru Nishizaki

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4097

Abstract: An example apparatus includes: first and second sense amplifier regions arranged such that the memory mat is sandwiched between the first and second sense amplifier regions in a first direction, the first and second sense amplifier regions including first and second sense amplifiers, respectively; and first and second array control circuit regions arranged in the first direction, the first and second array control circuit regions including first and second array control circuits configured to control the first and second sense amplifiers, respectively. Each of the first and second array control circuit regions includes a first well region in which a first circuit part of each of the first and second array control circuits are arranged, respectively. The first well region of the first array control circuit region and the first well region of the second array control circuit region are integrated.

公开(公告)号：US20250037754A1

公开(公告)日：2025-01-30

申请号：US18749394

申请日：2024-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsunari Murayama ,  Mamoru Nishizaki ,  Manami Mizukane ,  Hidekazu Noguchi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: An example apparatus includes first and second memory cell arrays arranged in a first direction; and a plurality of first and second sub word line drivers, a plurality of main word line drivers, and a plurality of level shift circuits each arranged on an intermediate region between the first and second memory cell arrays. The first and second sub word line drivers are arranged in a second direction and along the first and second memory cell array, respectively. The main word line drivers are arranged in the second direction and adjacently along the plurality of second sub word line drivers. The level shift circuits are arranged in the second direction and adjacently along the plurality of first sub word line drivers. The level shift circuits are configured to provide voltage-level-shifted signals to the plurality of main word line drivers, respectively.

公开(公告)号：US20230352061A1

公开(公告)日：2023-11-02

申请号：US17733746

申请日：2022-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mamoru Nishizaki

IPC: G11C5/06 ,  G11C11/4091 ,  H01L27/108

CPC classification number: G11C5/063 ,  G11C11/4091 ,  H01L27/10897 ,  G11C11/4094

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first bit line extending in a first direction, a first sense amplifier configured to amplify a potential of the first bit line, and a first transistor configured to supply an operation voltage to the first sense amplifier when a first control signal supplied to a gate electrode of the first transistor is activated. The first wiring layer further includes a first pattern coupled to the gate electrode of the first transistor and a second pattern having a first section arranged between the first bit line and the first pattern in a second direction perpendicular to the first direction.

公开(公告)号：US10896718B2

公开(公告)日：2021-01-19

申请号：US16656870

申请日：2019-10-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mamoru Nishizaki

IPC: G11C11/40 ,  G11C11/4074 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/06

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first power line extending in a first direction, a second wiring layer including second and third power lines extending in a second direction, a third wiring layer including power electrode patterns arranged in the second direction, and a fourth wiring layer including a fourth power line extending in the second direction. The first and second power lines are connected by a first via electrode. The first and third power lines are connected by a second via electrode. The second power line and each of the power electrode patterns are connected by a third via electrode. The third power line and each of the power electrode patterns are connected by a fourth via electrode. The fourth power line and each of the power electrode patterns are connected by a fifth via electrode.