公开(公告)号：US20240028248A1

公开(公告)日：2024-01-25

申请号：US17868085

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Christina Papagianni ,  Zhenming Zhou ,  Ting Luo

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604

Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.

公开(公告)号：US20240020025A1

公开(公告)日：2024-01-18

申请号：US18372998

申请日：2023-09-26

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Jian Huang ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0655

Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.

公开(公告)号：US20230393991A1

公开(公告)日：2023-12-07

申请号：US17842278

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

IPC: G06F12/1027 ,  G06F12/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/10

CPC classification number: G06F12/1027 ,  G06F12/0692 ,  G11C16/26 ,  G11C16/349 ,  G11C16/10 ,  G06F2212/68 ,  G11C16/0483

Abstract: A read command is received by a processing device coupled to a memory device. The read command specified a logical address. The processing device translates the logical address into a physical address of a physical block of the memory device, wherein the physical address specifies a wordline and a memory device die. Responsive to determining that the physical block is partially programmed, the processing device identifies a threshold voltage offset associated with the wordline. The processing device computes a modified threshold voltage by applying the threshold voltage offset to a read level associated with the memory device die. The processing device reads the data from the physical block using the modified threshold voltage.

公开(公告)号：US11762589B2

公开(公告)日：2023-09-19

申请号：US17396386

申请日：2021-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/32 ,  G01K13/00 ,  G11C7/06 ,  G11C7/22 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G01K13/00 ,  G06F3/0604 ,  G06F3/0679 ,  G11C7/06 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3404 ,  G11C16/0483

Abstract: A current operating characteristic value of a unit of the memory device is identified. An operating characteristic threshold value is identified from a set of operating characteristic thresholds, where the current operating characteristic value satisfies an operating characteristic threshold criterion that is based on the operating characteristic threshold value. A set of write-to-read (W2R) delay time thresholds that corresponds to the operating characteristic threshold value is identified from a plurality of sets of W2R delay time thresholds. Each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level. A W2R delay time threshold associated with a W2R delay time threshold criterion is identified from the set of W2R delay time thresholds, where the W2R threshold criterion is satisfied by a current W2R delay time of the memory sub-system. A read voltage level associated with the identified W2R delay time threshold is identified.

公开(公告)号：US11740959B2

公开(公告)日：2023-08-29

申请号：US16925215

申请日：2020-07-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/04 ,  G06F11/10 ,  G11C16/10 ,  G11C29/00

CPC classification number: G06F11/10 ,  G11C16/10 ,  G11C29/72

Abstract: An initial level of sensing voltage is set based on one or more characteristics of the segment of the memory device. A count for operational cycles for a segment of a memory device is set. Responsive to determining that a number of operational cycles performed on the segment of the memory device has reached the set count of operational cycles, the sensing voltage is varied with respect to the initial level of sensing voltage. The sensing voltage is adjusted to a new level based on wearing of the segment of the memory device during the number of operational cycles performed on the segment of the memory device.

公开(公告)号：US11721381B2

公开(公告)日：2023-08-08

申请号：US17393020

申请日：2021-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Li-Te Chang ,  Murong Lang ,  Zhongguang Xu ,  Zhenming Zhou

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074

CPC classification number: G11C11/40611 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/40622 ,  G11C11/40626

Abstract: A processing device of a memory sub-system is configured to determine a current refresh frequency associated with the memory device, the current refresh frequency specifying a rate of performing refresh operations on data stored at the memory device; compute an updated refresh frequency by updating the current refresh frequency based on a criterion reflecting a result of comparing one or more operating parameters of the memory device to their respective threshold values; and perform a refresh operation on data stored at the memory device according to the updated refresh frequency.

公开(公告)号：US11687248B2

公开(公告)日：2023-06-27

申请号：US17302851

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Tingjun Xie ,  Seungjune Jeon ,  Murong Lang ,  Zhenming Zhou

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/30

CPC classification number: G06F3/0616 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/3034

Abstract: Respective life expectancies of a first data unit and a second data unit of the memory device is obtained. A first initial age value corresponding to the first data unit and a second initial age value corresponding to the second data unit are determined. A lower one of the first initial age value and the second initial age value is identified. A first media management operation on a corresponding one of the first data unit or the second data unit associated with the lower one of the first initial age value and the second initial age value is performed. A second media management operation on the first data unit and the second data unit is performed.

公开(公告)号：US20230195354A1

公开(公告)日：2023-06-22

申请号：US17579923

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Yang Liu ,  Zhongguang Xu ,  Murong Lang ,  Fangfang Zhu

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0614 ,  G06F3/0679

Abstract: One or more media scan parameters associated with a memory device are maintained. A number of program erase cycles associated with the memory device is identified. Responsive to determining that the number of program erase cycles satisfies a criterion, one or more adjusted media scan parameters are generated by adjusting the one or more media scan parameters. A media scan of the memory device is performed according to the one or more adjusted media scan parameters.

公开(公告)号：US20230187009A1

公开(公告)日：2023-06-15

申请号：US17550462

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Murong Lang

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.

公开(公告)号：US20230062652A1

公开(公告)日：2023-03-02

申请号：US17463207

申请日：2021-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.