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    Integrated assemblies having shield lines between digit lines, and methods of forming integrated assemblies
    13.
    发明授权
    Integrated assemblies having shield lines between digit lines, and methods of forming integrated assemblies 有权

    公开(公告)号：US11069687B2

    公开(公告)日：2021-07-20

    申请号：US16809924

    申请日：2020-03-05

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

    IPC: H01L27/108

    Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

    Memory arrays
    15.
    发明授权
    Memory arrays 有权

    公开(公告)号：US10950618B2

    公开(公告)日：2021-03-16

    申请号：US16204224

    申请日：2018-11-29

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Richard J. Hill ,  Yi Fang Lee ,  Martin C. Roberts

    IPC: H01L27/11582 ,  H01L27/11585 ,  H01L27/11514 ,  G06F3/06

    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.

    Integrated Assemblies Having Charge-Trapping Material Arranged in Vertically-Spaced Segments, and Methods of Forming Integrated Assemblies
    17.
    发明申请
    Integrated Assemblies Having Charge-Trapping Material Arranged in Vertically-Spaced Segments, and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20200373325A1

    公开(公告)日：2020-11-26

    申请号：US16988548

    申请日：2020-08-07

    Applicant: Micron Technology, Inc.

    Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

    IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/08 ,  H01L21/02

    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

    MEMORY ARRAYS
    18.
    发明申请
    MEMORY ARRAYS 审中-公开

    公开(公告)号：US20200176465A1

    公开(公告)日：2020-06-04

    申请号：US16204224

    申请日：2018-11-29

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Richard J. Hill ,  Yi Fang Lee ,  Martin C. Roberts

    IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/11514 ,  H01L27/11585

    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.

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