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    Memory device clock swapping
    11.
    发明授权
    Memory device clock swapping 有权

    公开(公告)号：US12189414B2

    公开(公告)日：2025-01-07

    申请号：US17897957

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder ,  Navya Sri Sreeram ,  Scott E. Smith

    IPC: G06F1/08 ,  G06F1/10

    Abstract: An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.

    APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF
    13.
    发明公开
    APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF 审中-公开

    公开(公告)号：US20240160524A1

    公开(公告)日：2024-05-16

    申请号：US18504342

    申请日：2023-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

    IPC: G06F11/10

    CPC classification number: G06F11/1044

    Abstract: Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

    Internal data availability for system debugging
    15.
    发明授权
    Internal data availability for system debugging 有权

    公开(公告)号：US11710534B1

    公开(公告)日：2023-07-25

    申请号：US17682837

    申请日：2022-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Christian N. Mohr ,  Scott E. Smith ,  Manoj Vijay

    IPC: G11C29/52 ,  G11C29/02 ,  G11C29/46 ,  G11C29/00 ,  G11C29/12 ,  G11C29/38 ,  G11C29/04

    CPC classification number: G11C29/52 ,  G11C29/021 ,  G11C29/12005 ,  G11C29/38 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0409

    Abstract: Embodiments presented herein are directed to testing and/or debugging a memory device of a memory module (e.g., a dual in-line memory module (DIMM)) without having to remove the DIMM from a corresponding computing device and without having to interrupt operation of the computing device. A particular memory device (e.g., DRAM) may be identified for testing and/or debugging based on a failure message. However, the failure message may not identify a specific location or hardware of the module that caused the failure. Embodiments presented herein provide techniques to obtain data for analysis to determine and/or deliver a cause of the failure while reducing or eliminating downtime of the computing device. Test modes to do so may include a synchronous test mode, an asynchronous test mode, and an analog compare mode. A test mode may be selected based on the failure or a signal/function of the DRAM to be tested or debugged.

    SEMICONDUCTOR DEVICES HAVING THROUGH-STACK INTERCONNECTS FOR FACILITATING CONNECTIVITY TESTING
    16.
    发明申请
    SEMICONDUCTOR DEVICES HAVING THROUGH-STACK INTERCONNECTS FOR FACILITATING CONNECTIVITY TESTING 有权

    公开(公告)号：US20230037349A1

    公开(公告)日：2023-02-09

    申请号：US17965561

    申请日：2022-10-13

    Applicant: Micron Technology, Inc.

    Inventor： Christian N. Mohr ,  Scott E. Smith

    IPC: H01L25/065 ,  G01R27/14 ,  H01L23/538

    Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.

    ROW CLEAR FEATURES FOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS
    17.
    发明申请
    ROW CLEAR FEATURES FOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20220375507A1

    公开(公告)日：2022-11-24

    申请号：US17881482

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Miles S. Wiscombe ,  Scott E. Smith ,  Gary L. Howe ,  Brian W. Huber ,  Tony M. Brewer

    IPC: G11C11/408 ,  G11C11/4096 ,  G11C11/406

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

    ROW CLEAR FEATURES FOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS
    18.
    发明申请
    ROW CLEAR FEATURES FOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20220068349A1

    公开(公告)日：2022-03-03

    申请号：US17005034

    申请日：2020-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Miles S. Wiscombe ,  Scott E. Smith ,  Gary L. Howe ,  Brian W. Huber ,  Tony M. Brewer

    IPC: G11C11/408 ,  G11C11/4096 ,  G11C11/406

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

    Apparatuses and methods for decoding addresses for memory
    19.
    发明授权
    Apparatuses and methods for decoding addresses for memory 有权

    公开(公告)号：US11031083B2

    公开(公告)日：2021-06-08

    申请号：US16249714

    申请日：2019-01-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Gary L. Howe ,  Scott E. Smith

    IPC: G11C8/00 ,  G11C16/08 ,  G11C7/06 ,  G11C8/10

    Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

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