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11.发明申请公开(公告)号：US20250140322A1
公开(公告)日：2025-05-01
申请号：US18768974
申请日：2024-07-10
Applicant: Micron Technology, Inc.
Inventor： Shyam Sunder Raghunathan , Yingda Dong , Akira Goda , Leo Raimondo
Abstract: Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.
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公开(公告)号：US20250006269A1
公开(公告)日：2025-01-02
申请号：US18647554
申请日：2024-04-26
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Zhenming Zhou , Shyam Sunder Raghunathan , Tingjun Xie
Abstract: A processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of a block addressable by a first wordline of a first die of the memory device, wherein the first die comprises a plurality of decks of the memory device. The processing device identifies, based on a predefined usage type associated with the first die, a deck of the plurality of decks for performing the programming operation; and performing the programming operation on a second set of cells of the block addressable by the first wordline residing on the identified deck of the first die.
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公开(公告)号：US20240312529A1
公开(公告)日：2024-09-19
申请号：US18602960
申请日：2024-03-12
Applicant: Micron Technology, Inc.
Inventor： Karan Banerjee , Waing Pyie Soe , Shyam Sunder Raghunathan
CPC classification number: G11C16/26 , G11C16/0433 , G11C16/08
Abstract: Control logic in a memory device receives a request to perform a corrective read operation on one or more memory cells associated with a selected wordline of a memory array of a memory device and determines whether one or more memory cells associated with an adjacent wordline of the memory array are in an erased state. Responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state, the control logic identifies a partial block read voltage offset value and causes a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline.
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公开(公告)号：US20180190347A1
公开(公告)日：2018-07-05
申请号：US15907826
申请日：2018-02-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shyam Sunder Raghunathan , Pranav Kalavade , Krishna K. Parat , Charan Srinivasan
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.
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15.发明申请公开(公告)号：US20250087275A1
公开(公告)日：2025-03-13
申请号：US18768970
申请日：2024-07-10
Applicant: Micron Technology, Inc.
Inventor： Shyam Sunder Raghunathan , Yingda Dong , Akira Goda
Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.
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Patent Agency Ranking
公开(公告)号：US12224016B2
公开(公告)日：2025-02-11
申请号：US17888781
申请日：2022-08-16
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Karan Banerjee , Shyam Sunder Raghunathan
IPC: G11C16/26
Abstract: A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.
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公开(公告)号：US20250006292A1
公开(公告)日：2025-01-02
申请号：US18440619
申请日：2024-02-13
Applicant: Micron Technology, Inc.
Inventor： Taylor Alu , Nicola Ciocchini , Shyam Sunder Raghunathan , Guang Hu , Walter Di Francesco , Umberto Siciliani , Violante Moschiano , Karan Banerjee
Abstract: A method includes detecting a change in a memory control signal of a memory device including memory blocks, determining based at least on the change in the memory control signal that the memory device is in a stable state, and responsive to determining that the memory device is in the stable state, associating a voltage offset bin with at least one memory block of the memory device.
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公开(公告)号：US20250006275A1
公开(公告)日：2025-01-02
申请号：US18749198
申请日：2024-06-20
Applicant: Micron Technology, Inc.
Inventor： Shyam Sunder Raghunathan , Akira Goda , Kishore K. Muchherla
Abstract: An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. Control circuitry can be configured to: receive a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block; and determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation. The adjusted sense voltage is based on: a quantity of the first group of access lines that are programmed; or a quantity of the second group of access lines that are programmed; or both.
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公开(公告)号：US20240168880A1
公开(公告)日：2024-05-23
申请号：US18386783
申请日：2023-11-03
Applicant: Micron Technology, Inc.
Inventor： Akira Goda , Niccolo' Righetti , Shyam Sunder Raghunathan , Leo Raimondo , Kishore K. Muccherla
IPC: G06F12/02
CPC classification number: G06F12/0246
Abstract: An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. A controller is configured to monitor a cumulative amount of read disturb stress experienced by a first erase block by: maintaining a read disturb count corresponding to the first erase block; incrementing the read disturb count by a first amount responsive to read commands issued to addresses corresponding to the first erase block; incrementing the read disturb count by a read disturb scaling factor responsive to read commands issued to addresses corresponding to the second erase block; and incrementing the read disturb count by a program scaling factor responsive to program commands issued to addresses corresponding to the second erase block. The controller can perform an action on the first erase block responsive to the read disturb count exceeding a threshold value.
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公开(公告)号：US09396791B2
公开(公告)日：2016-07-19
申请号：US14334946
申请日：2014-07-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shyam Sunder Raghunathan , Pranav Kalavade , Krishna K. Parat , Charan Srinivasan
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.
Abstract translation: 提供了用于编程具有多级通过信号的存储器的存储器和方法。 一种方法包括将选择要编程的存储器的单元编程为存储器的特定目标数据状态，使用程序干扰来编程选择要编程的存储器的单元，以在编程期间将目标数据状态低于特定目标数据状态 将存储器的单元选择为被编程到特定目标数据状态，以及将选择要编程的存储器的单元的通道电压提升到低于特定目标数据状态的目标数据状态。 升压可能包括使用多步通过信号。
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