公开(公告)号：US20250004789A1

公开(公告)日：2025-01-02

申请号：US18747227

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Keng Gee Ng ,  Mohammed Musaiyab Tarapati ,  Shyam Sunder Raghunathan

IPC: G06F9/4401

Abstract: Control logic in a memory device initiates application of a program pulse on a memory array of a memory device as part of a program operation and determines whether a first request to suspend the program operation was received during the application of the program pulse. Responsive to determining that the first request to suspend the program operation was received during the application of the program pulse, the control logic sets a program suspend indicator to a suspend state. Responsive to completing application of the program pulse, the control logic initiates a program verify operation on the memory array, and responsive to completing the program verify operation, determines that the program suspend indicator is set to the suspend state and suspends the program operation.

公开(公告)号：US20240168878A1

公开(公告)日：2024-05-23

申请号：US18386746

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.

公开(公告)号：US20220342813A1

公开(公告)日：2022-10-27

申请号：US17302064

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Giuseppina Puzzilli ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  James Fitzpatrick ,  Shyam Sunder Raghunathan ,  Violante Moschiano ,  Tecla Ghilardi

IPC: G06F12/02 ,  G11C29/52 ,  G11C16/34

Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.

公开(公告)号：US20250157549A1

公开(公告)日：2025-05-15

申请号：US19022744

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Karan Banerjee ,  Shyam Sunder Raghunathan

IPC: G11C16/26

Abstract: A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.

公开(公告)号：US20250104781A1

公开(公告)日：2025-03-27

申请号：US18973880

申请日：2024-12-09

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Shyam Sunder Raghunathan ,  Walter Di Francesco

IPC: G11C16/32 ,  G11C16/08 ,  G11C16/10

Abstract: A memory device includes an array of memory cells associated with multiple wordlines and control logic operatively coupled with the array. The control logic, in performing a read operation, can determine a length of time that a selected wordline, of the multiple wordlines, takes to reach a pass voltage for reading data from a memory cell associated with the selected wordline. The control logic can select a delay time based on whether the length of time is associated with a transient state or a non-transient state. The control logic can read the data from the memory cell associated with the selected wordline after the selected delay time.

公开(公告)号：US20240168879A1

公开(公告)日：2024-05-23

申请号：US18386760

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

公开(公告)号：US20230197169A1

公开(公告)日：2023-06-22

申请号：US18083304

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Shyam Sunder Raghunathan ,  Walter Di Francesco

IPC: G11C16/32 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/32 ,  G11C16/102 ,  G11C16/08

Abstract: A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.

公开(公告)号：US10043574B2

公开(公告)日：2018-08-07

申请号：US15907826

申请日：2018-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/12

Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.

公开(公告)号：US09922704B2

公开(公告)日：2018-03-20

申请号：US15189178

申请日：2016-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427

Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.

公开(公告)号：US20250140323A1

公开(公告)日：2025-05-01

申请号：US18781524

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Kishore K. Muchherla ,  Hong Lu ,  Akira Goda ,  Shyam Sunder Raghunathan ,  Peter Feeley ,  Emilio Camerlenghi ,  Paolo Tessariol

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08

Abstract: An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.