公开(公告)号：US06295236B1

公开(公告)日：2001-09-25

申请号：US09553128

申请日：2000-04-19

Applicant: Martin Brox ,  Karl-Peter Pfefferl

Inventor： Martin Brox ,  Karl-Peter Pfefferl

IPC: G11C700

CPC classification number: G11C29/70

Abstract: The semiconductor memory of the random access type has data lines, which can be connected to the local data lines in the memory cell array. The data lines are combined in groups and at least one group or individual data lines of the groups are formed by redundant data lines. Input/output lines lead from the memory in groups. A bus system organized in two planes is provided. The first plane is provided with bus lines which can be connected to all of the input/output lines, on the one hand, and to all of the data lines, on the other hand. The second plane has a plurality of individual partial buses, whose bus lines can be connected to in each case all of the data lines of at least two groups of data lines, on the one hand, and to all of the input/output lines of in each case one group, on the other hand.

Abstract translation: 随机存取类型的半导体存储器具有可连接到存储单元阵列中的本地数据线的数据线。 数据线被组合成组，且组中的至少一个组或各个数据线由冗余数据线形成。 输入/输出线从组中的内存引出。 提供组织在两个飞机上的总线系统。 另一方面，第一平面设置有可以连接到所有输入/输出线路以及所有数据线路的总线。 第二平面具有多个单独的部分总线，其总线可以在每种情况下连接至少两组数据线的所有数据线，一方面连接到所有输入/输出线 另一方面，在每种情况下都是一组。

公开(公告)号：US6160747A

公开(公告)日：2000-12-12

申请号：US322718

申请日：1999-05-28

Applicant: Martin Brox ,  Helmut Schneider ,  Thomas Vogelsang ,  Michael Killian

Inventor： Martin Brox ,  Helmut Schneider ,  Thomas Vogelsang ,  Michael Killian

IPC: G11C8/08 ,  G11C11/408 ,  G11C7/00

CPC classification number: G11C11/4085 ,  G11C8/08

Abstract: A configuration for crosstalk attenuation in substantially mutually parallel word lines of DRAM circuits, includes a decoder provided at a first end of a word line, and a holding transistor. A pull-down device is provided as a "noise killer" at a second end of the word line, which opposite the first end. The pull-down device pulls down the potential of the word line in a standby and hold mode in the event of an active adjacent word line.

Abstract translation: 在DRAM电路的基本相互平行的字线中的串扰衰减的配置包括设置在字线的第一端的解码器和保持晶体管。 在与第一端相对的字线的第二端处提供下拉装置作为“噪声抑制器”。 在有效的相邻字线的情况下，下拉装置在待机和保持模式下拉下字线的电位。

公开(公告)号：US5881013A

公开(公告)日：1999-03-09

申请号：US884081

申请日：1997-06-27

Applicant: Martin Brox ,  Franz Freimuth ,  Mike Killian ,  Naokazu Miyawaki ,  Thilo Schaffroth

Inventor： Martin Brox ,  Franz Freimuth ,  Mike Killian ,  Naokazu Miyawaki ,  Thilo Schaffroth

IPC: G11C11/41 ,  G11C5/14 ,  G11C7/20 ,  G11C7/22 ,  G11C11/401

CPC classification number: G11C7/22 ,  G11C5/143 ,  G11C7/20

Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

公开(公告)号：US5847986A

公开(公告)日：1998-12-08

申请号：US992379

申请日：1997-12-17

Applicant: Martin Brox

Inventor： Martin Brox

IPC: G11C11/41 ,  G11C7/18 ,  G11C11/401 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC classification number: G11C7/18 ,  G11C11/409

Abstract: The spacing of the bit lines and/or the master bit lines (MBLs) of a memory array is skewed to decrease the charging current required to precharge the bit-lines and or the master bit lines. In one embodiment of the invention, an integrated circuit (IC) includes an array of memory cells arranged in rows and columns, with a pair of bit lines (BLTi and BLCi) per column of memory cells with BLTi carrying the cell data and BLCi its complement. The bit lines are disposed within a first level of the IC and run generally parallel to each other wherein there is a certain capacitance, CINT, between each two paired bit lines (BLTi and BLCi) and a capacitance, CEXT, between the bit lines of adjacent columns. The bit lines are coupled to selected MBLs with the MBLs being paired so that one MBL of a pair (MBLT) carries bit line data and the other MBL of a pair (MBLC) carries the complement of that bit line data. The MBLs are formed on a second level of the IC and run generally parallel to each other wherein there is a capacitance (MCINT) between the two paired master bit lines and a capacitance (MCEXT) between the master bit lines of a pair and the adjacent master bit lines. The spacing between the bit lines is skewed in order to decrease CINT relative to CEXT, and/or the spacing between the MBLs is skewed in order to decrease MCINT relative to MCEXT.

Abstract translation: 存储器阵列的位线和/或主位线（MBL）的间隔偏斜以减小对位线和/或主位线预充电所需的充电电流。 在本发明的一个实施例中，集成电路（IC）包括排列成行和列的存储单元阵列，每列具有携带单元数据的BLTi的存储单元的一对位线（BLTi和BLCi）和BLCi 补充。 位线布置在IC的第一电平内并且大致平行地彼此平行地运行，其中在每两个成对位线（BLTi和BLCi）之间存在一定电容CINT，并且位线之间的电容CEXT 相邻列。 位线被耦合到选择的MBL，其中MBL被配对，使得一对MBL（MBLT）携带位线数据，而另一个MBL（MBLC）携带该位线数据的补码。 MBL形成在IC的第二级，并且大体上彼此平行地运行，其中在两个成对主位线之间存在电容（MCINT），并且在一对主位线和相邻的主位线之间存在电容（MCEXT） 主位线。 位线之间的间距偏斜以相对于CEXT降低CINT，和/或MBL之间的间距倾斜，以便相对于MCEXT降低MCINT。

公开(公告)号：US20110205828A1

公开(公告)日：2011-08-25

申请号：US12710800

申请日：2010-02-23

Applicant: Michael Richter ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Peter Gregorius ,  Thomas Hein ,  Andreas Schneider

Inventor： Michael Richter ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Peter Gregorius ,  Thomas Hein ,  Andreas Schneider

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087

Abstract: A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.

Abstract translation: 一种半导体存储器，包括设置在集成电路上的多个存储体，每个存储体包括存储单元阵列，其中多个存储体的存储单元的第一部分具有第一存取速度和第二部分存储单元 多个存储器组具有第二存取速度，其中第一存取速度与第二存取速度不同。

公开(公告)号：US07855463B2

公开(公告)日：2010-12-21

申请号：US11853995

申请日：2007-09-12

Applicant: Martin Brox ,  Simon Muff

Inventor： Martin Brox ,  Simon Muff

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/13 ,  H01L23/49838 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: An integrated circuit module comprises a chip, the chip comprising a substrate with a first main area and a second main area, the first main area comprising two half-sets of pads, the chip further comprising an integrated circuit with components and two half-sets of connection lines, the connection lines connecting the components of the integrated circuit to the pads, the integrated circuit further comprising a changeover device, the changeover device having two switching states in order to interchange the electrical assignment between the half-sets of the connection lines and the half-sets of the pads, and a carrier, the carrier comprising contact pieces. The chip is arranged on the carrier with one of the two main areas of the chip facing the carrier and the contact pieces of the carrier are connected to the pads of the chip, wherein one of the two switching states of the changeover device is selected, depending on which of the two main areas of the chip is the area facing the carrier.

Abstract translation: 集成电路模块包括芯片，芯片包括具有第一主区域和第二主区域的基板，第一主区域包括两个半组焊盘，该芯片还包括具有部件和两个半组的集成电路 的连接线，将集成电路的部件连接到焊盘的连接线，该集成电路还包括切换装置，该切换装置具有两个切换状态，以便互换连接线半组之间的电气分配 和半组焊盘，以及载体，载体包括接触片。 芯片布置在载体上，芯片的两个主要区域中的一个面向载体，并且载体的接触片连接到芯片的焊盘，其中选择切换装置的两个切换状态之一， 取决于芯片的两个主要区域中哪一个是面向载体的区域。

公开(公告)号：US07746724B2

公开(公告)日：2010-06-29

申请号：US11669848

申请日：2007-01-31

Applicant: Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

Inventor： Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

IPC: G11C8/00

CPC classification number: G06F12/1416 ,  G06F13/4278 ,  G11C7/22 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method and apparatus for accessing a memory device. The method includes providing control signals for an access command to the memory device via an asynchronous interface and transmitting data for the access command to the memory device. The method also includes encoding, into the transmitted data, a clock signal. The encoded clock signal in the transmitted data is used by the memory device for receiving the data transmission.

Abstract translation: 一种用于访问存储器件的方法和装置。 该方法包括通过异步接口向存储器件提供访问命令的控制信号，并向存储器件发送访问命令的数据。 该方法还包括将数据编码到发送的数据中的时钟信号。 发送数据中的编码时钟信号被存储器装置用于接收数据传输。

公开(公告)号：US07482849B2

公开(公告)日：2009-01-27

申请号：US11211084

申请日：2005-08-25

Applicant: Martin Brox ,  Alessandro Minzoni

Inventor： Martin Brox ,  Alessandro Minzoni

IPC: H03L7/06

CPC classification number: H03K5/135

Abstract: The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device (101) to be used with the synchronization of clock signals (CLK, DQS), comprising: a delay means (102) with a variably controllable delay time (tvar), in which a clock signal (CLK) or a signal obtained therefrom is input, is loaded with the variably controllable delay time (tvar), and is output as delayed clock signal, a phase comparator (104) for comparing the phase of the clock signal (CLK) or of the signal obtained therefrom with the phase of the delayed clock signal or of a signal obtained therefrom (DCLK, FB), characterized in that additionally a means (401, 116) is provided for activating and/or deactivating said clock signal synchronizing device (101) as a function of control signals (RD) evaluated by an evaluating means (402).

Abstract translation: 本发明涉及一种时钟信号同步方法以及与时钟信号（CLK，DQS）的同步一起使用的时钟信号同步装置（101），包括：具有可变可控延迟时间的延迟装置（102） 输入时钟信号（CLK）或从其获得的信号的tvar）被加载可变可控延迟时间（tvar），并作为延迟时钟信号输出，相位比较器（104）用于比较 时钟信号（CLK）或由其获得的延迟时钟信号的相位或由其获得的信号（DCLK，FB）获得的信号的信号，其特征在于，还提供了用于激活和/或执行的装置（401,116） 作为由评估装置（402）评估的控制信号（RD）的函数，去激活所述时钟信号同步装置（101）。

公开(公告)号：US20080252346A1

公开(公告)日：2008-10-16

申请号：US11735748

申请日：2007-04-16

Applicant: Martin Brox

Inventor： Martin Brox

IPC: H03L7/00

CPC classification number: H03L7/0814 ,  H03L7/095

Abstract: A circuit having a clock signal synchronizing device with capability to filter clock-jitters is disclosed. One embodiment provides a delayed locked loop with capability to filter clock-jitter. Further, the invention relates to a clock signal synchronizing method with capability to filter clock-jitter.

Abstract translation: 公开了具有能够对时钟抖动进行滤波的时钟信号同步装置的电路。 一个实施例提供了具有滤波时钟抖动能力的延迟锁定环。 此外，本发明涉及具有滤波时钟抖动能力的时钟信号同步方法。

公开(公告)号：US20080191790A1

公开(公告)日：2008-08-14

申请号：US10585151

申请日：2004-11-23

Applicant: Martin Brox

Inventor： Martin Brox

IPC: G05F1/10 ,  G05F3/02

CPC classification number: G05F1/465

Abstract: One aspect of the invention relates to a voltage regulation process as well as to a voltage regulation system. A first voltage, present at an input of the voltage regulating system, is changed into a second voltage, which can be tapped at an output of the voltage regulation systems, with a first device for generating an essentially constant voltage from the first voltage, or a voltage derived from it. A further device is provided for generating a further voltage from the first voltage or a voltage derived from it, in particular a voltage which can be higher than the voltage generated by the first devices.

Abstract translation: 本发明的一个方面涉及电压调节过程以及电压调节系统。 存在于电压调节系统的输入处的第一电压被改变成可以在电压调节系统的输出处被抽头的第二电压，其中第一电压用于从第一电压产生基本上恒定的电压，或 来自它的电压。 提供了另外的装置，用于从第一电压或从其导出的电压产生另外的电压，特别是可以高于由第一装置产生的电压的电压。