公开(公告)号：US08373239B2

公开(公告)日：2013-02-12

申请号：US12795962

申请日：2010-06-08

申请人： Shahab Siddiqui ,  Michael P. Chudzik ,  Carl J. Radens

发明人： Shahab Siddiqui ,  Michael P. Chudzik ,  Carl J. Radens

IPC分类号： H01L21/70

CPC分类号： H01L29/66575 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

公开(公告)号：US20120181616A1

公开(公告)日：2012-07-19

申请号：US13006642

申请日：2011-01-14

申请人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.

摘要翻译： 提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。 等离子体氮化的nFET阈值电压调节的高k栅介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化的pFET阈值电压调节的高k栅介质层部分包括多达15个 原子％N2和位于其中的pFET阈值电压调节物质。

公开(公告)号：US08643115B2

公开(公告)日：2014-02-04

申请号：US13006642

申请日：2011-01-14

申请人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC分类号： H01L27/092

CPC分类号： H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.

摘要翻译： 提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。 等离子体氮化的nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分包括多达15个 原子％N2和位于其中的pFET阈值电压调节物质。

公开(公告)号：US20110298061A1

公开(公告)日：2011-12-08

申请号：US12795962

申请日：2010-06-08

申请人： Shahab Siddiqui ,  Michael P. Chudzik ,  Carl J. Radens

发明人： Shahab Siddiqui ,  Michael P. Chudzik ,  Carl J. Radens

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

摘要翻译： 本公开提供了一种用于形成半导体器件的方法，其包括形成覆盖在衬底的沟道区上的替代栅极结构。 在衬底的源极和漏极区域上形成心轴介电层。 去除替代栅极结构以提供暴露衬底的沟道区的开口。 在包括功函数金属层的沟道区域上形成功能栅极结构。 在功能栅极结构上形成保护帽结构。 通过对保护盖结构有选择性的心轴介质层蚀刻至少一个通孔，以暴露源极区域和漏极区域中的至少一个的一部分。 然后在通孔中形成导电填充物以提供与源极区域和漏极区域中的至少一个的接触。

公开(公告)号：US08836037B2

公开(公告)日：2014-09-16

申请号：US13584156

申请日：2012-08-13

申请人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

发明人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L27/088

CPC分类号： H01L21/28185 ,  H01L21/02181 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

摘要翻译： 有限数量的Hi-K材料的原子层沉积（ALD）循环，然后沉积层间电介质并施加另外的Hi-K材料并且可选但优选的退火提供了增加的Hi-K材料含量和增加的输入的击穿电压 与输入/输出（I / O）晶体管相比，与同一芯片或晶圆上形成的逻辑晶体管相比，同时提供I / O和逻辑晶体管的反型层的可扩展性，而不会明显地影响性能或偏置温度不稳定性（BTI）参数。

公开(公告)号：US20140042546A1

公开(公告)日：2014-02-13

申请号：US13584156

申请日：2012-08-13

申请人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

发明人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L27/088

CPC分类号： H01L21/28185 ,  H01L21/02181 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

摘要翻译： 有限数量的Hi-K材料的原子层沉积（ALD）循环，然后沉积层间电介质并施加另外的Hi-K材料并且可选但优选的退火提供了增加的Hi-K材料含量和增加的输入的击穿电压 与输入/输出（I / O）晶体管相比，与同一芯片或晶圆上形成的逻辑晶体管相比，同时提供I / O和逻辑晶体管的反型层的可扩展性，而不会明显地影响性能或偏置温度不稳定性（BTI）参数。

公开(公告)号：US08431476B2

公开(公告)日：2013-04-30

申请号：US13570980

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

公开(公告)号：US20120171818A1

公开(公告)日：2012-07-05

申请号：US13418716

申请日：2012-03-13

申请人： Karl W. Barth ,  Ricardo A. Donaton ,  Spyridon Galis ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ricardo A. Donaton ,  Spyridon Galis ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L21/50

CPC分类号： H01L23/5389 ,  H01L21/76898 ,  H01L24/80 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2924/12044

摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

摘要翻译： 第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。 凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。 第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。 第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。 通过基底通孔（TSV）结构通过键合介电材料部分形成。 位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。

公开(公告)号：US20090117360A1

公开(公告)日：2009-05-07

申请号：US11933760

申请日：2007-11-01

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Habib Hichri ,  Louis L. Hsu ,  Kaushik A. Kumar ,  Carl Radens ,  Shahab Siddiqui ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Habib Hichri ,  Louis L. Hsu ,  Kaushik A. Kumar ,  Carl Radens ,  Shahab Siddiqui ,  Chih-Chao Yang

IPC分类号： G03C1/73 ,  B05D3/00 ,  B32B27/06

CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  H01L21/0338

摘要： A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.

摘要翻译： 含有至少两个不混溶的聚合物嵌段组分的非光敏聚合物抗蚀剂沉积在平面上。 将非光敏聚合物抗蚀剂退火以允许不相容组分的相分离并显影以除去至少两种聚合物嵌段组分中的至少一种。 在聚合物抗蚀剂中形成纳米尺度特征，即纳米尺度的特征，包括具有纳米级尺寸的至少一个凹陷区域。 聚合物抗蚀剂的顶表面通过暴露于能量束而被改进以提高耐蚀刻性，这允许图案化聚合物抗蚀剂的顶表面变得更耐蚀刻工艺和化学物质。 两种类型表面之间的增强的耐蚀刻比提供了改善的图像对比度和具有顶表面和至少一个凹陷区域的区域之间的保真度。

公开(公告)号：US20090001592A1

公开(公告)日：2009-01-01

申请号：US11770928

申请日：2007-06-29

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了形成金属互连的方法和包括金属互连的IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。