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公开(公告)号：US08422273B2
公开(公告)日：2013-04-16
申请号：US12470159
申请日：2009-05-21
IPC分类号： G11C11/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
摘要翻译： 提供了基于纳米线的场效应晶体管（FET）及其制造技术。 在一个方面，提供了一种FET，其具有在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源区和漏区的多个纳米线通道，其中一个或多个 的器件层被配置为具有来自一个或多个其它器件层的不同阈值电压; 以及围绕纳米线通道的每个器件层共用的栅极。
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12.发明申请SEMICONDUCTOR DEVICE INCLUDING AN ASYMMETRIC FEATURE, AND METHOD OF MAKING THE SAME 有权包括不对称特征的半导体器件及其制造方法公开(公告)号：US20130026465A1
公开(公告)日：2013-01-31
申请号：US13194980
申请日：2011-07-31
申请人： Josephine Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey Sleight
发明人： Josephine Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey Sleight
IPC分类号： H01L27/088 , H01L21/336 , H01L29/66
CPC分类号： H01L29/7835 , H01L21/823425 , H01L21/823475 , H01L21/823814 , H01L21/823871 , H01L27/088 , H01L29/41775 , H01L29/66659 , H01L29/7845
摘要： A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.
摘要翻译： 具有不对称特征的半导体器件（例如，场效应晶体管（FET））包括形成在衬底上的第一栅极，形成在第一栅极一侧的衬底中的第一和第二扩散区域以及第一和第二触点， 分别与第一和第二扩散区接触，第一触点相对于第二触点是不对称的。
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公开(公告)号：US20120138888A1
公开(公告)日：2012-06-07
申请号：US13316515
申请日：2011-12-11
IPC分类号： H01L27/088 , H01L29/775 , B82Y99/00
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译： 提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区 掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。
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公开(公告)号：US20110309334A1
公开(公告)日：2011-12-22
申请号：US12820341
申请日：2010-06-22
申请人： Josephine Chang , Isaac Lauer , Jeffrey Sleight
发明人： Josephine Chang , Isaac Lauer , Jeffrey Sleight
CPC分类号： H01L29/66628 , B82Y10/00 , H01L21/76897 , H01L29/0665 , H01L29/0669 , H01L29/1606 , H01L29/66742 , H01L29/778 , H01L29/78684 , H01L51/0048 , H01L51/0508
摘要： A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.
摘要翻译： 一种用于形成场效应晶体管（FET）的方法，包括在衬底上沉积沟道材料，所述沟道材料包括石墨烯或纳米结构之一; 在所述通道材料的第一部分上形成栅极; 形成邻近门的间隔物; 在沟道材料，栅极和间隔物上沉积接触材料; 在所述接触材料上沉积介电材料; 去除介电材料的一部分和接触材料的一部分以暴露栅极的顶部; 使接触材料凹陷; 去除介电材料; 以及图案化所述接触材料以形成所述FET的自对准接触，所述自对准接触位于所述FET的源极区域和漏极区域之上，所述源极区域和所述漏极区域包括所述沟道材料的第二部分 。
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公开(公告)号：US20100295021A1
公开(公告)日：2010-11-25
申请号：US12470128
申请日：2009-05-21
IPC分类号： H01L29/15 , H01L21/336 , H01L27/12
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译： 提供基于纳米线的设备。 一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。
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16.发明申请公开(公告)号：US20090108373A1
公开(公告)日：2009-04-30
申请号：US11927964
申请日：2007-10-30
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108
摘要： Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
摘要翻译： 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。
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公开(公告)号：US08946680B2
公开(公告)日：2015-02-03
申请号：US13571657
申请日：2012-08-10
IPC分类号： H01L29/72 , H01L29/06 , B82Y10/00 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H01L29/739 , H01L29/78 , H01L29/40
CPC分类号： H01L29/0847 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0895 , H01L29/402 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66977 , H01L29/7391 , H01L29/775 , H01L29/78 , H01L29/78618 , H01L29/78696 , Y10S977/723 , Y10S977/938
摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
摘要翻译： 隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。
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公开(公告)号：US20120299107A1
公开(公告)日：2012-11-29
申请号：US13571734
申请日：2012-08-10
申请人： Leland Chang , Isaac Lauer , Jeffrey Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey Sleight
IPC分类号： H01L27/12
CPC分类号： H01L21/823807 , H01L29/7847
摘要： A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.
摘要翻译： 包括高性能器件区域和高密度器件区域的CMOS芯片包括在高性能器件区域中包括n型场效应晶体管（NFET）和p型场效应晶体管（PFET）的多个高性能器件，其中 高性能器件具有高性能间距; 以及在高密度器件区域中包括NFET和PFET的多个高密度器件，其中高密度器件具有高密度间距，并且其中高性能间距是高密度间距的约2至3倍; 其中所述高性能器件区域包括掺杂源极和漏极区域，具有使用应力记忆技术（SMT），栅极硅化物和源极/漏极硅化物区域引起的升高的应力的NFET栅极区域和双重应力衬里，并且其中所述高密度器件 区域包括掺杂源极和漏极区，栅极硅化物区域和中性应力衬里。
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公开(公告)号：US08216902B2
公开(公告)日：2012-07-10
申请号：US12536741
申请日：2009-08-06
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译： 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。
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公开(公告)号：US08084308B2
公开(公告)日：2011-12-27
申请号：US12470128
申请日：2009-05-21
IPC分类号： H01L21/00 , H01L21/84 , H01L27/148 , H01L27/105
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译： 提供基于纳米线的设备。 一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。
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