公开(公告)号：US11152039B2

公开(公告)日：2021-10-19

申请号：US16508753

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli

IPC: G06F13/00 ,  G11C7/08 ,  G06F13/16 ,  G06F3/06 ,  G11C7/10 ,  G11C8/10 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08

Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.

公开(公告)号：US20140095774A1

公开(公告)日：2014-04-03

申请号：US14098054

申请日：2013-12-05

Applicant: Micron Technology Inc.

Inventor： Massimiliano Mollichelli ,  Andrea Martinelli ,  Stefan Schippers

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F8/66

Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.

Abstract translation: 本文所描述的示例性实施例可以包括至少部分地响应于代码获取地址和存储在陷阱地址寄存器中的地址之间的匹配而将非易失性存储器设备内的固件执行转移到一个或多个替换指令。

公开(公告)号：US20240393961A1

公开(公告)日：2024-11-28

申请号：US18794482

申请日：2024-08-05

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent

IPC: G06F3/06

Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.

公开(公告)号：US20240321349A1

公开(公告)日：2024-09-26

申请号：US18622033

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71

Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

公开(公告)号：US11915740B2

公开(公告)日：2024-02-27

申请号：US17686240

申请日：2022-03-03

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC: G11C8/00 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093

CPC classification number: G11C11/4082 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093

Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

公开(公告)号：US20230307041A1

公开(公告)日：2023-09-28

申请号：US17655957

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71

Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

公开(公告)号：US11740678B2

公开(公告)日：2023-08-29

申请号：US17573194

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Graziano Mirichigni

IPC: G06F1/32 ,  G06F9/44 ,  G06F1/3225 ,  G06F1/3234 ,  G06F9/4401 ,  G06F1/3287

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/4401

Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

公开(公告)号：US20230245701A1

公开(公告)日：2023-08-03

申请号：US17588718

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Andrea Ghetti ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi ,  Paolo Fantini

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0028 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/003 ,  G11C13/0004 ,  G11C2213/30 ,  G11C2213/15

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. Two current limiters are each used on the digit line side of each memory cell. A negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. A negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. A positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. The current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.

公开(公告)号：US20230071663A1

公开(公告)日：2023-03-09

申请号：US17943591

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Andrea Martinelli ,  Claudio Nava

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

公开(公告)号：US11217291B2

公开(公告)日：2022-01-04

申请号：US16508772

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Francesco Mastroianni ,  Kiyoshi Nakai

IPC: G11C7/08 ,  G11C7/12 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.