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    TECHNIQUES FOR MANUFACTURING A DOUBLE ELECTRODE MEMORY ARRAY
    15.
    发明申请
    TECHNIQUES FOR MANUFACTURING A DOUBLE ELECTRODE MEMORY ARRAY 有权

    公开(公告)号：US20230113960A1

    公开(公告)日：2023-04-13

    申请号：US17499709

    申请日：2021-10-12

    Applicant: Micron Technology, Inc.

    Inventor： Anna Maria Conti ,  Andrea Gotti ,  Pavan Reddy K. Aella

    IPC: H01L27/24 ,  H01L45/00

    Abstract: Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.

    Three-dimensional memory array
    16.
    发明授权
    Three-dimensional memory array 有权

    公开(公告)号：US11574957B2

    公开(公告)日：2023-02-07

    申请号：US17320785

    申请日：2021-05-14

    Applicant: Micron Technology, Inc.

    Inventor： Anna Maria Conti ,  Andrea Redaelli ,  Agostino Pirovano

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.

    Self-aligned memory decks in cross-point memory arrays
    17.
    发明授权
    Self-aligned memory decks in cross-point memory arrays 有权

    公开(公告)号：US11489117B2

    公开(公告)日：2022-11-01

    申请号：US17308444

    申请日：2021-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

    SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS
    18.
    发明申请
    SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS 有权

    公开(公告)号：US20210328142A1

    公开(公告)日：2021-10-21

    申请号：US17308444

    申请日：2021-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

    Memory cells with asymmetrical electrode interfaces
    19.
    发明授权
    Memory cells with asymmetrical electrode interfaces 审中-公开

    公开(公告)号：US10672981B2

    公开(公告)日：2020-06-02

    申请号：US16706358

    申请日：2019-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Anna Maria Conti ,  Fabio Pellizzer

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

    SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS
    20.
    发明申请
    SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS 审中-公开

    公开(公告)号：US20200075858A1

    公开(公告)日：2020-03-05

    申请号：US16665955

    申请日：2019-10-28

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

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