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    Semiconductor layered device with data bus
    12.
    发明授权
    Semiconductor layered device with data bus 有权

    公开(公告)号：US11120849B2

    公开(公告)日：2021-09-14

    申请号：US16459439

    申请日：2019-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Chikara Kondo ,  Chiaki Dono

    IPC: G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  G06F13/42

    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.

    SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS
    13.
    发明申请
    SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS 审中-公开

    公开(公告)号：US20190325926A1

    公开(公告)日：2019-10-24

    申请号：US16459439

    申请日：2019-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Chikara Kondo ,  Chiaki Dono

    IPC: G11C7/10 ,  G11C5/02 ,  G11C7/22 ,  G06F13/42 ,  G11C5/06

    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.

    APPARATUSES AND METHODS FOR PROVIDING MULTIPHASE CLOCK SIGNALS
    14.
    发明申请
    APPARATUSES AND METHODS FOR PROVIDING MULTIPHASE CLOCK SIGNALS 审中-公开

    公开(公告)号：US20190214061A1

    公开(公告)日：2019-07-11

    申请号：US16357700

    申请日：2019-03-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Homare Sato ,  Chiaki Dono ,  Chikara Kondo

    IPC: G11C7/22 ,  H03K3/037

    CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03K3/037 ,  H03K5/15013

    Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.

    SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS
    15.
    发明申请
    SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS 审中-公开

    公开(公告)号：US20190034370A1

    公开(公告)日：2019-01-31

    申请号：US16150505

    申请日：2018-10-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Chikara Kondo ,  Akinori Funahashi

    IPC: G06F13/40 ,  G11C29/36 ,  G11C29/12 ,  G11C7/10 ,  H03M13/29

    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.

    Semiconductor layered device with data bus
    16.
    发明授权
    Semiconductor layered device with data bus 有权

    公开(公告)号：US10146719B2

    公开(公告)日：2018-12-04

    申请号：US15468742

    申请日：2017-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Chikara Kondo ,  Akinori Funahashi

    IPC: G06F13/40 ,  G11C7/10 ,  H03M13/29 ,  G11C29/12 ,  G11C29/36

    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.

    MEMORY DEVICE WITH WRITE DATA BUS CONTROL
    17.
    发明申请
    MEMORY DEVICE WITH WRITE DATA BUS CONTROL 审中-公开

    公开(公告)号：US20180151207A1

    公开(公告)日：2018-05-31

    申请号：US15365563

    申请日：2016-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

    IPC: G11C8/18 ,  G11C7/10 ,  G11C19/28

    CPC classification number: G11C7/1087 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C19/28 ,  G11C2207/108 ,  G11C2207/2272

    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

    Semiconductor device including spiral data path
    18.
    发明授权
    Semiconductor device including spiral data path 有权
    半导体器件包括螺旋数据路径

    公开(公告)号：US09472253B2

    公开(公告)日：2016-10-18

    申请号：US14607858

    申请日：2015-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Seiji Narui ,  Chikara Kondo

    IPC: G11C7/22 ,  G11C5/02 ,  G11C7/10 ,  H01L25/065 ,  G11C5/06 ,  G11C11/4097

    CPC classification number: G11C7/22 ,  G11C5/02 ,  G11C5/063 ,  G11C7/10 ,  G11C11/4097 ,  H01L25/0657 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal.

    Abstract translation: 本公开中公开的半导体器件包括形成在半导体衬底的第一表面上的第一端子，形成在与第一表面相对的半导体衬底的第二表面上方的第二端子，穿过半导体的第一贯穿衬底通孔（TSV） 基板和先进先出（FIFO）电路，其中第一TSV和FIFO电路串联耦合在第一端子和第二端子之间。

    SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CIRCUITRY
    19.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CIRCUITRY 有权

    公开(公告)号：US20250118386A1

    公开(公告)日：2025-04-10

    申请号：US18789680

    申请日：2024-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Shadden Kerstetter ,  Raghukiran Sreeramaneni ,  Nevil N. Gajera ,  Chikara Kondo

    IPC: G11C29/36 ,  G11C7/10

    Abstract: Disclosed are methods, systems, and apparatuses for a memory device with test circuitry-based processing-in-memory (PIM). The memory device utilizes circuitry used to control, sequence, and/or perform test functions, found on a die of the memory device (e.g., an interface die and/or memory die), to perform PIM functions. For example, the memory device may utilize a memory built-in self-test (mBIST) automatic pattern generator (APG) for PIM sequencing. To control PIM operations, the mBIST APG may fetch and decode microcode instructions local to the die. The microcode instructions may be fetched from a read-only memory (ROM) and/or non-volatile memory. Microcode instructions to perform desired PIM operations may be written to the non-volatile memory by a host device coupled to the memory device.

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