公开(公告)号：US10600796B2

公开(公告)日：2020-03-24

申请号：US15624422

申请日：2017-06-15

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Jason C. McFarland ,  Jason Reece ,  David A. Kewley ,  Adam L. Olson

IPC: H01L21/3213 ,  H01L27/11556 ,  H01L21/311 ,  H01L27/11582 ,  G03F7/00

Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.

公开(公告)号：US20190103350A1

公开(公告)日：2019-04-04

申请号：US16200902

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： William R. Brown ,  Jenna L. Russon ,  Tim H. Bossart ,  Brian R. Watson ,  Nikolay A. Mirin ,  David A. Kewley

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/108

Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.

公开(公告)号：US09178077B2

公开(公告)日：2015-11-03

申请号：US13675933

申请日：2012-11-13

Applicant: Micron Technology, Inc.

Inventor： Neal L. Davis ,  David A. Kewley

IPC: H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions.

Abstract translation: 一些实施例包括具有堆叠的半导体结构，所述堆叠包含交替的控制栅极材料和中间介电材料。 通道材料面板沿着第一方向延伸穿过堆叠。 所述面板将所述堆叠分成所述面板的第一侧上的第一部分和所述面板的第二侧上的第二部分。 存储单元堆叠在通道材料面板和控制栅极材料之间。 存储单元堆叠包括形状为具有指向通道材料面板的开口端的容器的单元电介质材料，并且在容器内包括电荷存储材料。 一些实施例包括形成半导体结构的方法。

公开(公告)号：US20140131784A1

公开(公告)日：2014-05-15

申请号：US13675933

申请日：2012-11-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Neal L. Davis ,  David A. Kewley

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions.

Abstract translation: 一些实施例包括具有堆叠的半导体结构，所述堆叠包含交替的控制栅极材料和中间介电材料。 通道材料面板沿着第一方向延伸穿过堆叠。 所述面板将所述堆叠分成所述面板的第一侧上的第一部分和所述面板的第二侧上的第二部分。 存储单元堆叠在通道材料面板和控制栅极材料之间。 存储单元堆叠包括形状为具有指向通道材料面板的开口端的容器的单元电介质材料，并且在容器内包括电荷存储材料。 一些实施例包括形成半导体结构的方法。

公开(公告)号：US20250120085A1

公开(公告)日：2025-04-10

申请号：US18985534

申请日：2024-12-18

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US11990367B2

公开(公告)日：2024-05-21

申请号：US17444948

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yongjun J. Hu ,  David A. Kewley ,  Md Zahid Hossain ,  Michael J. Irwin ,  Daniel Billingsley ,  Suresh Ramarajan ,  Robert J. Hanson ,  Biow Hiem Ong ,  Keen Wah Chow

IPC: H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76804

Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

公开(公告)号：US20230371282A1

公开(公告)日：2023-11-16

申请号：US17742154

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： David A. Kewley ,  Kevin Baker ,  Trupti D. Gawai

IPC: H01L27/24 ,  G11C13/00

CPC classification number: H01L27/2463 ,  G11C13/0023 ,  G11C2213/77

Abstract: Integrated circuitry comprises a horizontally-elongated insulative wall directly above a conductive node. The wall comprises insulative material. A conductive via extends through the wall to the conductive node. A conductive line is directly above the wall and directly above the conductive via. The conductive via directly electrically couples together the conductive line with the conductive node. Insulator material is longitudinally-along laterally-opposing sides of the wall. An interface of the insulative material of the wall and the insulator material are on each of the laterally-opposing sides of the wall. Other embodiments, including method, are disclosed.

公开(公告)号：US20230165004A1

公开(公告)日：2023-05-25

申请号：US18158576

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US20230021072A1

公开(公告)日：2023-01-19

申请号：US17947038

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20220077177A1

公开(公告)日：2022-03-10

申请号：US17016002

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.