-
公开(公告)号：US20210020239A1
公开(公告)日：2021-01-21
申请号：US17062127
申请日：2020-10-02
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Paolo Amato , Federico Pio , Alessandro Orlando , Marco Sforzin
Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
-
公开(公告)号：US10452541B2
公开(公告)日：2019-10-22
申请号：US16162266
申请日：2018-10-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Federico Pio
Abstract: Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of a data block is stored in the phase change memory and a second portion of the data block is stored in the FLASH memory. The first portion of the data block is accessed prior to the second portion of the data block during a read operation.
-
13.发明授权Method for making three dimensional memory array architecture using phase change and ovonic switching materials 有权使用相变和二次开关材料制作三维存储阵列结构的方法公开(公告)号：US09252362B2
公开(公告)日：2016-02-02
申请号：US14470247
申请日：2014-08-27
Applicant: Micron Technology, Inc.
Inventor： Federico Pio
CPC classification number: H01L45/06 , H01L27/0688 , H01L27/10 , H01L27/101 , H01L27/224 , H01L27/2427 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/1683
Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.
Abstract translation: 提供三维记忆阵列及其形成方法。 示例性三维存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部，使得 至少一个导电延伸部与多个第一导线中的至少一个的一部分相交。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。
-
公开(公告)号：US09076524B2
公开(公告)日：2015-07-07
申请号：US14283117
申请日：2014-05-20
Applicant: Micron Technology, Inc.
Inventor： Federico Pio
IPC: G11C16/06 , G11C14/00 , G11C16/26 , G11C16/04 , G11C16/12 , G06F21/60 , G11C5/14 , G11C16/30 , G11C7/22 , G11C7/10 , G11C11/56
CPC classification number: G11C5/147 , G06F12/0246 , G06F21/60 , G06F2212/7204 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C11/5621 , G11C11/5671 , G11C14/0063 , G11C14/009 , G11C16/0408 , G11C16/06 , G11C16/107 , G11C16/12 , G11C16/26 , G11C16/30
Abstract: A method is provided for accessing a memory device. The method includes programming data in a plurality of cells of the memory device in a first programming operation. The first programming operation uses a first memory instruction including at least one first parameter representative of at least one first threshold voltage value for said programming. The method further includes re-programming at least a portion of the data in the plurality of cells in a second programming operation. The second programming operation uses a second memory instruction including at least one second parameter representative of at least one second threshold voltage value for said re-programming, wherein said re-programming provides bit manipulation of the portion of the data.
Abstract translation: 提供了一种访问存储器件的方法。 该方法包括在第一编程操作中在存储器件的多个单元中编程数据。 第一编程操作使用包括代表用于所述编程的至少一个第一阈值电压值的至少一个第一参数的第一存储器指令。 该方法还包括在第二编程操作中对多个单元中的数据的至少一部分进行重新编程。 第二编程操作使用包括表示用于所述重新编程的至少一个第二阈值电压值的至少一个第二参数的第二存储器指令，其中所述重新编程提供对所述数据的该部分的位操作。
-
15.发明申请METHOD OF USING MEMORY INSTRUCTION INCLUDING PARAMETER TO AFFECT OPERATING CONDITION OF MEMORY 有权使用存储器指令（包括参数）影响存储器的操作条件的方法公开(公告)号：US20140250280A1
公开(公告)日：2014-09-04
申请号：US14283117
申请日：2014-05-20
Applicant: Micron Technology, Inc.
Inventor： Federico Pio
IPC: G11C14/00
CPC classification number: G11C5/147 , G06F12/0246 , G06F21/60 , G06F2212/7204 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C11/5621 , G11C11/5671 , G11C14/0063 , G11C14/009 , G11C16/0408 , G11C16/06 , G11C16/107 , G11C16/12 , G11C16/26 , G11C16/30
Abstract: A method is provided for accessing a memory device. The method includes programming data in a plurality of cells of the memory device in a first programming operation. The first programming operation uses a first memory instruction including at least one first parameter representative of at least one first threshold voltage value for said programming. The method further includes re-programming at least a portion of the data in the plurality of cells in a second programming operation. The second programming operation uses a second memory instruction including at least one second parameter representative of at least one second threshold voltage value for said re-programming, wherein said re-programming provides bit manipulation of the portion of the data.
Abstract translation: 提供了一种访问存储器件的方法。 该方法包括在第一编程操作中在存储器件的多个单元中编程数据。 第一编程操作使用包括代表用于所述编程的至少一个第一阈值电压值的至少一个第一参数的第一存储器指令。 该方法还包括在第二编程操作中对多个单元中的数据的至少一部分进行重新编程。 第二编程操作使用包括表示用于所述重新编程的至少一个第二阈值电压值的至少一个第二参数的第二存储器指令，其中所述重新编程提供对所述数据的该部分的位操作。
-
Patent Agency Ranking
公开(公告)号：US20230121141A1
公开(公告)日：2023-04-20
申请号：US18083963
申请日：2022-12-19
Applicant: Micron Technology, Inc.
Inventor： Federico Pio
IPC: H01L21/56 , H01L21/78 , H01L23/28 , H01L23/00 , H01L23/544
Abstract: Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) an indication positioned in a designated area of the first surface. The indication includes a code presenting information for operating the semiconductor die. The code is configured to be read by an indication scanner coupled to a controller.
-
公开(公告)号：US20200035297A1
公开(公告)日：2020-01-30
申请号：US16536120
申请日：2019-08-08
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Paolo Amato , Federico Pio , Alessandro Orlando , Marco Sforzin
Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
-
公开(公告)号：US09595667B2
公开(公告)日：2017-03-14
申请号：US15011816
申请日：2016-02-01
Applicant: Micron Technology, Inc.
Inventor： Federico Pio
CPC classification number: H01L45/06 , H01L27/0688 , H01L27/10 , H01L27/101 , H01L27/224 , H01L27/2427 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/1683
Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.
Abstract translation: 提供三维记忆阵列及其形成方法。 示例性三维存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部，使得 至少一个导电延伸部与多个第一导线中的至少一个的一部分相交。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。
-
19.发明授权公开(公告)号：US08728856B2
公开(公告)日：2014-05-20
申请号：US13748221
申请日：2013-01-23
Applicant: Micron Technology, Inc.
Inventor： Federico Pio
IPC: H01L21/00
CPC classification number: H01L45/1286 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/16 , H01L45/1675
Abstract: A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.
Abstract translation: 用于相变存储器的基本上平面的加热器可以向上延伸以逐渐接触硫族化物层。 结果，加热器和硫族化物之间的接触面积减小了。 在一些实施例中，这种减小的接触面积可以降低功耗。
-
公开(公告)号：US12277969B2
公开(公告)日：2025-04-15
申请号：US18661300
申请日：2024-05-10
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Paolo Amato , Federico Pio , Alessandro Orlando , Marco Sforzin
Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
-
-
-
-
-
-
-
-
-
Search Results
42
records
(took 0.018 seconds)
