中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

56 records (took 0.017 seconds)

    Peak power management in a memory device
    11.
    发明授权
    Peak power management in a memory device 有权

    公开(公告)号：US11928343B2

    公开(公告)日：2024-03-12

    申请号：US17983177

    申请日：2022-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Jonathan Scott Parry ,  Luigi Pilolli

    IPC: G06F3/06 ,  G06F12/0802

    CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60

    Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

    METHODS TO LIMIT POWER DURING STRESS TEST AND OTHER LIMITED SUPPLIES ENVIRONMENT
    16.
    发明申请
    METHODS TO LIMIT POWER DURING STRESS TEST AND OTHER LIMITED SUPPLIES ENVIRONMENT 有权

    公开(公告)号：US20220199190A1

    公开(公告)日：2022-06-23

    申请号：US17125503

    申请日：2020-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Jonathan Scott Parry ,  Deping He ,  Giuseppe Cariello

    IPC: G11C29/50 ,  G11C5/14 ,  G11C29/56

    Abstract: A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

    Storage system deep idle power mode
    17.
    发明授权
    Storage system deep idle power mode 有权

    公开(公告)号：US11216058B2

    公开(公告)日：2022-01-04

    申请号：US16511490

    申请日：2019-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Qing Liang ,  Jonathan Scott Parry

    IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/28

    Abstract: Systems and methods are disclosed, including, after a first threshold time after entering an idle power mode of a storage system, without receiving a command from a host device over a communication interface, moving host data stored in volatile memory of the storage system to non-volatile memory of the storage system and transitioning a power mode of the storage system from an idle power mode to a deep idle power mode using control circuitry of the storage system, the deep idle power mode having a second power level lower than a first power level of the idle mode and a second exit latency higher than a first latency of the idle mode. The control circuitry can further determine that the storage system is ready to enter a power savings power mode and provide an indication of the determination using a unidirectional power state signal interface separate from the communication interface.

    HOST ASSISTED OPERATIONS IN MANAGED MEMORY DEVICES
    18.
    发明申请
    HOST ASSISTED OPERATIONS IN MANAGED MEMORY DEVICES 有权

    公开(公告)号：US20210056044A1

    公开(公告)日：2021-02-25

    申请号：US16544337

    申请日：2019-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Nadav Grosz ,  Jonathan Scott Parry

    IPC: G06F12/14 ,  G06F12/02 ,  G06F21/78

    Abstract: Devices and techniques for efficient host assisted logical-to-physical (L2P) mapping are described herein. For example, a command can be executed that results in a change as to which physical address of a memory device corresponds to a logical address. The change can be obfuscated as part of an obfuscated L2P map for the memory device and written to storage on the memory device. The change can then be provided a host from the storage.

Patent Agency Ranking