公开(公告)号：US20230236931A1

公开(公告)日：2023-07-27

申请号：US17894886

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Amitava Majumdar ,  Sandeep Krishna Thirumala ,  Nevil Gajera

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0689

Abstract: Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.

公开(公告)号：US11694747B2

公开(公告)日：2023-07-04

申请号：US17337806

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Xuan Anh Tran ,  Karthik Sarpatwari ,  Francesco Douglas Verna-Ketel ,  Jessica Chen ,  Nevil N. Gajera ,  Amitava Majumdar

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0092

Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.

公开(公告)号：US20230195624A1

公开(公告)日：2023-06-22

申请号：US17556891

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Sandeep Krishna Thirumala ,  Lingming Yang ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60 ,  G06F2212/72

Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.

公开(公告)号：US20220351759A1

公开(公告)日：2022-11-03

申请号：US17306562

申请日：2021-05-03

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Jessica Chen ,  Lingming Yang

IPC: G11C7/10

Abstract: Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.

公开(公告)号：US20250123976A1

公开(公告)日：2025-04-17

申请号：US18789660

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Raghukiran Sreeramaneni ,  Nevil N. Gajera

IPC: G06F13/18 ,  G06F13/16 ,  G06F13/42

Abstract: An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.

公开(公告)号：US11942139B2

公开(公告)日：2024-03-26

申请号：US18075570

申请日：2022-12-06

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Lingming Yang ,  Nevil N. Gajera ,  John Christopher M. Sancon

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

公开(公告)号：US11664074B2

公开(公告)日：2023-05-30

申请号：US17336913

申请日：2021-06-02

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  Yen Chun Lee ,  Jessica Chen ,  Francesco Douglas Verna-Ketel

IPC: G11C11/00 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/0483

Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.

公开(公告)号：US20230102468A1

公开(公告)日：2023-03-30

申请号：US18075570

申请日：2022-12-06

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Lingming Yang ,  Nevil N. Gajera ,  John Christopher M. Sancon

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4074

Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

公开(公告)号：US11616098B2

公开(公告)日：2023-03-28

申请号：US17833596

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera ,  Lei Wei

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L23/532

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

公开(公告)号：US11532347B2

公开(公告)日：2022-12-20

申请号：US17167922

申请日：2021-02-04

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Lingming Yang ,  Nevil N. Gajera ,  John Christopher M. Sancon

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4074

Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. A memory can include a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells. Circuitry is configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.