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    MICROELECTRONIC DEVICES INCLUDING TIERED STACKS INCLUDING CONDUCTIVE STRUCTURES ISOLATED BY SLOT STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS
    12.
    发明申请
    MICROELECTRONIC DEVICES INCLUDING TIERED STACKS INCLUDING CONDUCTIVE STRUCTURES ISOLATED BY SLOT STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS 有权

    公开(公告)号：US20220199641A1

    公开(公告)日：2022-06-23

    申请号：US17127971

    申请日：2020-12-18

    Applicant: Micron Technology, Inc.

    Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

    IPC: H01L27/11582 ,  H01L27/11556

    Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

    MEMORY DEVICE INCLUDING DIFFERENT DIELECTRIC STRUCTURES BETWEEN BLOCKS
    13.
    发明申请
    MEMORY DEVICE INCLUDING DIFFERENT DIELECTRIC STRUCTURES BETWEEN BLOCKS 有权

    公开(公告)号：US20250142831A1

    公开(公告)日：2025-05-01

    申请号：US19004725

    申请日：2024-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

    IPC: H10B43/50 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

    FORMING RESISTIVE RANDOM ACCESS MEMORIES TOGETHER WITH FUSE ARRAYS
    18.
    发明申请
    FORMING RESISTIVE RANDOM ACCESS MEMORIES TOGETHER WITH FUSE ARRAYS 有权
    形成电阻随机访问记忆与保险丝阵列

    公开(公告)号：US20150280123A1

    公开(公告)日：2015-10-01

    申请号：US14738453

    申请日：2015-06-12

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Umberto Maria Meotto ,  Giorgio Servalli

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L23/5256 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

    Abstract translation: 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。

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