公开(公告)号：US20240071515A1

公开(公告)日：2024-02-29

申请号：US18235183

申请日：2023-08-17

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Quang Diep ,  Avinash Rajagiri ,  Yingda Dong

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line. During the subset of erase loops, a first adjusted erase bias voltage is caused to be applied to the first select gate and a second adjusted erase bias voltage is caused to be applied to the second select gate.

公开(公告)号：US20230268003A1

公开(公告)日：2023-08-24

申请号：US18103978

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Vinh Quang Diep ,  Jeffrey Ming-Hung Tsai ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/3459 ,  G11C16/08 ,  G11C16/0483

Abstract: A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.

公开(公告)号：US11688471B2

公开(公告)日：2023-06-27

申请号：US17689862

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C11/00 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3436 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3413

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

公开(公告)号：US20220189555A1

公开(公告)日：2022-06-16

申请号：US17247576

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

公开(公告)号：US20220149068A1

公开(公告)日：2022-05-12

申请号：US17092916

申请日：2020-11-09

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Yan Song ,  Albert Fayrushin ,  Naiming Liu ,  Yingda Dong ,  George Matamis

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

公开(公告)号：US20220130475A1

公开(公告)日：2022-04-28

申请号：US17568797

申请日：2022-01-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.

公开(公告)号：US11238946B2

公开(公告)日：2022-02-01

申请号：US17078161

申请日：2020-10-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.

公开(公告)号：US11183245B1

公开(公告)日：2021-11-23

申请号：US16910789

申请日：2020-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic causes a second positive pre-boosting voltage to be applied to a second plurality of word lines of the data block during the pre-boosting phase, wherein the second plurality of word lines is adjacent to the first plurality of wordlines, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive pre-booting voltage has a lower magnitude than the first positive pre-boosting voltage. The control logic further causes the second positive pre-boosting voltage to be ramped down to a ground voltage during the pre-boosting phase prior to the first positive pre-boosting voltage being ramped down to the ground voltage.

公开(公告)号：US10854304B1

公开(公告)日：2020-12-01

申请号：US16701238

申请日：2019-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a first string of series-connected memory cells selectively connected to a first data line, applying a first voltage level to the access line for a second memory cell of the first string, applying a second voltage level higher than the first voltage level to the access line for the particular memory cell, applying a third voltage level to the first data line concurrently with applying the first voltage level and concurrently with applying the second voltage level, and applying a fourth voltage level higher than the third voltage level to a second data line selectively connected to a second string of series-connected memory cells concurrently with applying the third voltage level to the first data line.

公开(公告)号：US20240249776A1

公开(公告)日：2024-07-25

申请号：US18411532

申请日：2024-01-12

Applicant: Micron Technology, Inc.

Inventor： Vinh Quang Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/12

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/12

Abstract: A request to execute a programming operation to program a set of memory cells associated with a target wordline of a memory device is identified. At a first time during application of a programming voltage to the target wordline, causing a first adjusted pass through voltage to be applied to a first portion of a first set of drain-side wordlines of the memory device. At a second time during application of the programming voltage to the target wordline, causing a second pass through voltage to be applied to a second portion of the first set of drain-side wordlines and to one or more source-side wordlines of the memory device, where the first adjusted pass through voltage is greater than the second pass through voltage.