公开(公告)号：US10269819B2

公开(公告)日：2019-04-23

申请号：US15497009

申请日：2017-04-25

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Charles H. Dennison ,  Anish A. Khandekar ,  Brett D. Lowe ,  Lining He ,  Brian Cleereman

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

公开(公告)号：US10121799B2

公开(公告)日：2018-11-06

申请号：US15851532

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Tom J. John ,  Kunal Shrotri ,  Anish A. Khandekar ,  Aaron R. Wilson ,  John D. Hopkins ,  Derek F. Lundberg

IPC: H01L27/11582 ,  H01L21/033 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11556

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US11871582B2

公开(公告)日：2024-01-09

申请号：US17589310

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H10B53/20 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/223 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

CPC classification number: H10B53/20 ,  H01L21/223 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US20230307543A1

公开(公告)日：2023-09-28

申请号：US18195480

申请日：2023-05-10

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Sameer Chhajed ,  Jeffery B. Hull ,  Anish A. Khandekar

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04 ,  H10B12/00

CPC classification number: H01L29/7841 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/02686 ,  H01L29/04 ,  H10B12/20

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

公开(公告)号：US11264395B1

公开(公告)日：2022-03-01

申请号：US17027046

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11597 ,  H01L27/1159 ,  H01L29/10 ,  H01L21/223

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US20210351197A1

公开(公告)日：2021-11-11

申请号：US17385201

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/04

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US11011538B2

公开(公告)日：2021-05-18

申请号：US16406148

申请日：2019-05-08

Applicant: Micron Technology, inc.

Inventor： David H. Wells ,  Luan C. Tran ,  Jie Li ,  Anish A. Khandekar ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

公开(公告)号：US10749041B2

公开(公告)日：2020-08-18

申请号：US16659478

申请日：2019-10-21

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Kunal Shrotri ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Duo Mao ,  Zhixin Xu ,  Ee Ee Eng ,  Jie Li ,  Dong Liang

IPC: H01L29/792 ,  H01L27/1157 ,  H01L29/66 ,  H01L21/28 ,  G11C16/04 ,  G11C16/08

Abstract: A method of forming Si3Nx, where “x” is less than 4 and at least 3, comprises decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another, at least one of the at least two different decomposition species comprising Si. An outer substrate surface is contacted with the at least two decomposition species. At least one of the decomposition species that comprises Si attaches to the outer substrate surface to comprise an attached species. The attached species is contacted with a N-comprising precursor that reacts with the attached species to form a reaction product comprising Si3Nx, where “x” is less than 4 and at least 3. Other embodiments are disclosed, including constructions made in accordance with method embodiments of the invention and constructions independent of method of manufacture.

公开(公告)号：US20190371815A1

公开(公告)日：2019-12-05

申请号：US16437781

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/02

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US10483407B2

公开(公告)日：2019-11-19

申请号：US15957594

申请日：2018-04-19

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Kunal Shrotri ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Duo Mao ,  Zhixin Xu ,  Ee Ee Eng ,  Jie Li ,  Dong Liang

IPC: H01L21/28 ,  H01L27/1157 ,  H01L29/66 ,  G11C16/04 ,  G11C16/08 ,  H01L29/792

Abstract: A method of forming Si3Nx, where “x” is less than 4 and at least 3, comprises decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another, at least one of the at least two different decomposition species comprising Si. An outer substrate surface is contacted with the at least two decomposition species. At least one of the decomposition species that comprises Si attaches to the outer substrate surface to comprise an attached species. The attached species is contacted with a N-comprising precursor that reacts with the attached species to form a reaction product comprising Si3Nx, where “x” is less than 4 and at least 3. Other embodiments are disclosed, including constructions made in accordance with method embodiments of the invention and constructions independent of method of manufacture.