公开(公告)号：US20200321352A1

公开(公告)日：2020-10-08

申请号：US16907967

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US20200176471A1

公开(公告)日：2020-06-04

申请号：US16783981

申请日：2020-02-06

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20200020529A1

公开(公告)日：2020-01-16

申请号：US16582109

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Anish A. Khandekar ,  Kunal Shrotri ,  Jie Li

IPC: H01L21/02 ,  H01L27/115

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

公开(公告)号：US20180114795A1

公开(公告)日：2018-04-26

申请号：US15851532

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Tom J. John ,  Kunal Shrotri ,  Anish A. Khandekar ,  Aaron R. Wilson ,  John D. Hopkins ,  Derek F. Lundberg

IPC: H01L27/11582 ,  H01L21/033 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/11556 ,  H01L29/7883

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US20230292510A1

公开(公告)日：2023-09-14

申请号：US18198752

申请日：2023-05-17

Applicant: Micron Technology, Inc.

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunal Shrotri ,  Swapnil Lengade

IPC: H10B43/27 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3115 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/31111 ,  H01L21/3115 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11706924B2

公开(公告)日：2023-07-18

申请号：US17718863

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunal Shrotri ,  Swapnil Lengade

IPC: H10B43/27 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3115 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/022 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/3115 ,  H01L21/31111 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11621270B2

公开(公告)日：2023-04-04

申请号：US17385201

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US11476268B2

公开(公告)日：2022-10-18

申请号：US16887178

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Kunal Shrotri

IPC: H01L27/11556 ,  H01L27/11585 ,  H01L27/11519

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

公开(公告)号：US20210265171A1

公开(公告)日：2021-08-26

申请号：US17318470

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC: H01L21/311 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11582

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

公开(公告)号：US11094705B2

公开(公告)日：2021-08-17

申请号：US16518498

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/11568 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.