公开(公告)号：US20140021517A1

公开(公告)日：2014-01-23

申请号：US13551107

申请日：2012-07-17

申请人： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

发明人： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

摘要： A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 在衬底中形成隔离结构，并且在隔离结构的顶部形成栅叠层。 邻接栅叠层的侧壁并且延伸超出隔离结构的边缘的间隔件。 所公开的方法提供了通过使用间隔物来保护隔离结构的改进方法。 间隔件可以防止隔离结构被化学物质损坏，从而增强接触着陆和提升设备性能。

公开(公告)号：US08502316B2

公开(公告)日：2013-08-06

申请号：US12704367

申请日：2010-02-11

申请人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

发明人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

IPC分类号： H01L29/72

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

摘要翻译： 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。

公开(公告)号：US20110193179A1

公开(公告)日：2011-08-11

申请号：US12716100

申请日：2010-03-02

申请人： Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

发明人： Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848

摘要： An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 该方法包括提供基底; 在衬底上形成栅极结构; 在由栅极结构插入的衬底的源极和漏极区域中形成外延层; 并且在形成外延层之后，在源极和漏极区域中形成轻掺杂的源极和漏极（LDD）特征。

公开(公告)号：US08828817B2

公开(公告)日：2014-09-09

申请号：US13356207

申请日：2012-01-23

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC分类号： H01L21/8238

CPC分类号： H01L29/7849 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7613 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.

摘要翻译： 形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。 该方法还包括在衬底上形成第一应力膜。 该方法还包括对基板和第一应力膜执行第一退火处理。 该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。

公开(公告)号：US08053344B1

公开(公告)日：2011-11-08

申请号：US12886743

申请日：2010-09-21

申请人： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

发明人： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

IPC分类号： H01L29/00

CPC分类号： H01L21/2257 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

摘要翻译： 形成集成电路的方法包括在衬底上形成栅极结构。 在与栅极结构的侧壁相邻的源极/漏极（S / D）区域中形成至少一个含硅层。 在至少一个含硅层上形成N型掺杂含硅层。 N型掺杂含硅层的N型掺杂剂浓度高于至少一种含硅层。 对N型掺杂含硅层进行退火，以将N型掺杂含硅层的N型掺杂剂驱动到S / D区。

公开(公告)号：US08754477B2

公开(公告)日：2014-06-17

申请号：US13277872

申请日：2011-10-20

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/324 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78654

摘要： A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.

摘要翻译： 公开了一种制造方法和具有多个位错结构的半导体器件。 示例性半导体器件包括覆盖半导体衬底的顶表面的栅极结构和设置在栅极结构的侧壁上且覆盖衬底顶表面的第一栅极间隔。 半导体器件还包括结晶半导体材料，其覆盖半导体衬底的顶表面并与第一栅极间隔物的侧壁相邻。 半导体器件还包括设置在第一栅极间隔物的侧壁上并覆盖结晶的半导体材料的第二栅极间隔物。 半导体器件还包括设置在半导体衬底中的第一应力区域和设置在半导体衬底和晶体化半导体材料中的第二应力区域。

公开(公告)号：US20130099294A1

公开(公告)日：2013-04-25

申请号：US13280094

申请日：2011-10-24

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26593 ,  H01L21/76232 ,  H01L29/045 ,  H01L29/7833 ,  H01L29/7847

摘要： A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET.

摘要翻译： 一种方法包括形成金属氧化物半导体场效应晶体管（MOSFET），其包括形成与MOSFET的栅电极相邻的第一位错面，并形成与MOSFET的栅电极相邻的第二位错面。 第一和第二位错平面位于栅电极的同一侧，并延伸到MOSFET的源/漏区。

公开(公告)号：US20110193167A1

公开(公告)日：2011-08-11

申请号：US12704367

申请日：2010-02-11

申请人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

发明人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

IPC分类号： H01L27/12 ,  H01L27/105

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

摘要翻译： 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。

公开(公告)号：US09799750B2

公开(公告)日：2017-10-24

申请号：US13551107

申请日：2012-07-17

申请人： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

发明人： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

IPC分类号： H01L29/772 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

摘要： A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

公开(公告)号：US08809918B2

公开(公告)日：2014-08-19

申请号：US13280094

申请日：2011-10-24

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai

IPC分类号： H01L29/76

CPC分类号： H01L21/26506 ,  H01L21/26593 ,  H01L21/76232 ,  H01L29/045 ,  H01L29/7833 ,  H01L29/7847

摘要： A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET.

摘要翻译： 一种方法包括形成金属氧化物半导体场效应晶体管（MOSFET），其包括形成与MOSFET的栅电极相邻的第一位错面，并形成与MOSFET的栅电极相邻的第二位错面。 第一和第二位错平面位于栅电极的同一侧，并延伸到MOSFET的源/漏区。