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    ACTIVATED SLUDGE MATERIAL, METHOD FOR REDUCING EXCESS SLUDGE PRODUCTION IN BIOREACTOR, AND METHOD OF CONTROLLING BIOREACTOR
    12.
    发明申请
    ACTIVATED SLUDGE MATERIAL, METHOD FOR REDUCING EXCESS SLUDGE PRODUCTION IN BIOREACTOR, AND METHOD OF CONTROLLING BIOREACTOR 有权
    活性污泥材料，降低生物反应器中过剩污泥生产的方法，以及控制生物反应器的方法

    公开(公告)号：US20100206808A1

    公开(公告)日：2010-08-19

    申请号：US12675600

    申请日：2008-08-26

    申请人： Katsuhiko Maeda ,  Minoru Okamoto

    发明人： Katsuhiko Maeda ,  Minoru Okamoto

    IPC分类号： C02F3/12 ,  C12N9/24

    CPC分类号： C02F3/342 ,  C02F3/006 ,  C02F3/341 ,  C02F3/348 ,  C02F2103/20 ,  C02F2103/22 ,  C02F2103/26 ,  C02F2103/32 ,  C02F2209/36 ,  C02F2303/06

    摘要： Excess sludge production in a bioreactor of a wastewater treatment plant in which excess sludge is being produced is reduced by adding an activated sludge material having a chitinase specific activity of at least 150 Units/g-MLSS and a pectinase specific activity of at least 120 Units/g-MLSS to the bioreactor. After the addition of the activated sludge material, the bioreactor is controlled by adding the activated sludge material when any one of the chitinase activity, the pectinase activity, and the protease specific of the sludge in the bioreactor drops below the lower limits of 50 Units/L, 40 Units/L, and 0.3 Units/L, respectively.

    摘要翻译： 通过添加具有至少150单位/ g-MLSS的几丁质酶比活性和至少120单位的果胶酶特异性活性的活性污泥材料，可以减少生产过剩污泥的废水处理厂的生物反应器中的过剩污泥生产 / g-MLSS到生物反应器。 添加活性污泥材料后，生物反应器中的几丁质酶活性，果胶酶活性和污泥蛋白酶特异性中的任何一种下降到50单位/ L，40单位/ L，0.3单位/ L。

    Information contents download system
    13.
    发明授权
    Information contents download system 有权
    信息内容下载系统

    公开(公告)号：US07774281B2

    公开(公告)日：2010-08-10

    申请号：US11152085

    申请日：2005-06-15

    申请人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

    发明人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

    IPC分类号： G06F21/00

    CPC分类号： G06F21/10

    摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

    摘要翻译： 终端装置向内容发布装置发送其设备信息和获取信息内容的请求。 内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并发送使用实现功能所需的功能标准的许可请求 到许可证管理设备。 许可证管理装置接收使用许可证请求，并相应地向程序发布装置和内容分发装置发送使用功能标准的授权。 程序分发装置仅在接收到使用授权时将程序发送到终端装置。 内容分发装置仅在接收到使用授权时才将该信息内容发送到终端装置。

    Method of configuring information processing system and semiconductor integrated circuit
    14.
    发明授权
    Method of configuring information processing system and semiconductor integrated circuit 失效
    配置信息处理系统和半导体集成电路的方法

    公开(公告)号：US07536289B2

    公开(公告)日：2009-05-19

    申请号：US11071465

    申请日：2005-03-04

    申请人： Kazuhiro Okabayashi ,  Minoru Okamoto

    发明人： Kazuhiro Okabayashi ,  Minoru Okamoto

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.

    摘要翻译： 一种根据本发明的信息处理系统的配置方法，在用于实现一个或多个应用的​​信息处理系统中，包括：对于每个确定的处理级别并输入模型的所有应用进行建模的步骤，步骤 输入表示输入模型的不变性的参数的步骤，使用应用模型和表示不变性的参数作为输入信息并将表示不变性的参数与边界条件进行比较的步骤，以及将应用模型之一分配给可编程 逻辑和另一个应用模型基于比较结果的专用硬件。

    RECONFIGURABLE SEMICONDUCTOR INTERGRATED CIRCUIT AND PROCESSING ASSIGNMENT METHOD FOR THE SAME
    15.
    发明申请
    RECONFIGURABLE SEMICONDUCTOR INTERGRATED CIRCUIT AND PROCESSING ASSIGNMENT METHOD FOR THE SAME 有权
    可重构半导体集成电路及其加工分配方法

    公开(公告)号：US20080061834A1

    公开(公告)日：2008-03-13

    申请号：US11667302

    申请日：2006-10-02

    申请人： Tatsuya Tetsukawa ,  Minoru Okamoto ,  Shinichi Marui

    发明人： Tatsuya Tetsukawa ,  Minoru Okamoto ,  Shinichi Marui

    IPC分类号： H03K19/00

    CPC分类号： H03K19/1774 ,  G06F17/5054

    摘要： A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

    摘要翻译： 多个逻辑元件组LEG 11至LEG 33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组（例如LEG 11和LEG 12）之间，终端中的时钟输出端和时钟通过线连接，而终端中的数据输出端和数据通过延迟元件101连接。逻辑 元素组LEG 11至LEG 33在时序设计方面因此彼此独立。 因此，如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计，则可以仅设计新的电路并将其连接到现有的电路，或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。

    Programmable Logic Device and Method for Designing the Same
    16.
    发明申请
    Programmable Logic Device and Method for Designing the Same 有权
    可编程逻辑器件及其设计方法

    公开(公告)号：US20080042687A1

    公开(公告)日：2008-02-21

    申请号：US10581024

    申请日：2005-03-10

    申请人： Atsuhiro Mori ,  Shinichi Marui ,  Minoru Okamoto

    发明人： Atsuhiro Mori ,  Shinichi Marui ,  Minoru Okamoto

    IPC分类号： H03K19/177

    CPC分类号： H01L27/118

    摘要： The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced.In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.

    摘要翻译： 可以减少由可编程逻辑元件形成的可编程逻辑器件的功耗和面积。 在由可编程逻辑元件形成的可编程逻辑器件101中，提供了第一逻辑元件102和第二逻辑元件104，其具有与第一逻辑元件102相同的逻辑，但具有被设计为低于 第一逻辑元件102。

    Information processing apparatus and information processing method
    18.
    发明授权
    Information processing apparatus and information processing method 失效
    信息处理装置和信息处理方法

    公开(公告)号：US07058792B2

    公开(公告)日：2006-06-06

    申请号：US10485547

    申请日：2002-08-01

    申请人： Minoru Okamoto ,  Katsuhiko Ueda

    发明人： Minoru Okamoto ,  Katsuhiko Ueda

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30196 ,  G06F9/30181

    摘要： An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.

    摘要翻译： 一种用于顺序读取和执行存储在存储装置中的程序的信息处理装置，包括：程序计数器，用于将用于读取程序的地址输出到存储装置; 指令解码器，用于响应于指示在构成程序中的指令的至少一个字段中使用的代码的类型被限制为预定数量或更少的周期的控制信号来解码从存储器装置读取的指令; 以及用于执行与从指令解码器输出的解码结果对应的处理的控制装置。 指令解码器具有可重构电路，用于响应于控制信号改变电路配置，使得基于所使用的代码的类型的码中的码之间的关系进行解码，并且解码结果，该关系被设置 使得字段中比特值的改变次数减少。

    Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture
    20.
    发明授权
    Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture 有权
    用于控制和提供相位时钟信号到具有多处理器架构的集成电路的组件的装置

    公开(公告)号：US06928575B2

    公开(公告)日：2005-08-09

    申请号：US09973888

    申请日：2001-10-11

    申请人： Kazuhiro Okabayashi ,  Minoru Okamoto ,  Shinichi Marui

    发明人： Kazuhiro Okabayashi ,  Minoru Okamoto ,  Shinichi Marui

    IPC分类号： G11C7/22 ,  G06F1/12

    CPC分类号： G11C7/222 ,  G11C7/22

    摘要： A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.

    摘要翻译： 第一处理器，第二处理器，存储器和时钟提供单元在单个芯片上集成在一起。 第一个处理器与第一个内部时钟信号同步工作。 第二处理器与第二内部时钟信号同步工作。 存储器与第三个内部时钟信号同步工作。 时钟供应单元从外部时钟信号产生三个彼此同相的时钟信号，并将这些时钟信号作为第一，第二和第三内部时钟信号提供。 第一和第二处理器通过数据总线共享存储器。 每个处理器都有一个内部复位信号。